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TLIN1039DDFRQ1

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Texas Instruments LIN Transceivers, TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLIN1039DDFRQ1

Texas Instruments · LIN Transceivers · TSOT-23-8

TLIN1039DDFRQ1 from Texas Instruments, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXD output RXD is an open-drain output that reports the state of the LIN bus voltage to the microcontroller.
2 EN input Enable input: high puts the device in normal operation mode and low puts it in sleep mode, with an integrated pull-down.
3 NC unconnected Not connected.
4 TXD input TXD input controls the state of the LIN output, with an integrated pull-down.
5 GND power_in Ground terminal; all device voltages are specified with respect to this terminal.
6 LIN bidirectional LIN bus single-wire transmitter and receiver; the absolute maximum LIN bus input voltage is -45 V to 45 V (ISO 17987).
7 VSUP power_in Device supply voltage, connected to the battery through an external reverse-blocking diode; recommended operating range is 4.5 V to 36 V.
8 NC unconnected Not connected.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSOT-23-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VSUP Supply voltage range (ISO 17987) VSUP -0.3 45 V 5
LIN Bus input voltage (ISO 17987) VLIN -45 45 V 5
Logic input voltage (TXD, EN) VLOGIC_INPUT -0.3 6 V 5
Logic output voltage (RXD) VLOGIC_OUTPUT -0.3 6 V 5
Digital pin output current IO 8 mA 5
Junction Temp TJ -55 165 °C 5
Storage temperature Tstg -65 150 °C 5
Supply Voltage VSUP 4.5 36 V -40℃ ≤ TJ ≤ 150℃ 6
LIN bus input voltage VLIN 0 36 V -40℃ ≤ TJ ≤ 150℃ 6
Logic Pin Voltage VLOGIC 0 5.25 V -40℃ ≤ TJ ≤ 150℃ 6
Operating virtual junction temperature range TJ -40 150 °C -40℃ ≤ TJ ≤ 150℃ 6
Operational supply voltage (ISO 17987 Param 10) VSUP 4.5 36 V Device is operational beyond the LIN defined nominal supply voltage range; See 图 8-1 and 图 8-2 6
Nominal supply voltage (ISO 17987 Param 10) VSUP 4.5 36 V Normal and standby modes; See 图 8-1 and 图 8-2 6
Supply current, bus dominant, normal mode ISUP 1.2 6.5 mA EN = High, RLIN ≥ 500 Ω, CLIN ≤ 10 nF 6
Supply current, bus dominant, standby mode ISUP 1 1.7 mA EN = 0 V, RLIN ≥ 500 Ω, CLIN ≤ 10 nF 6
Supply current, bus recessive, normal mode ISUP 300 700 µA EN = High 6
Supply current, bus recessive, standby mode ISUP 20 30 µA EN = 0 V 6
Supply current, sleep mode (4.5 V < VSUP ≤ 14 V) ISUP 9 14 µA 4.5 V < VSUP ≤ 14 V, EN = 0 V, TXD and RXD floating 6
Supply current, sleep mode (14 V < VSUP ≤ 36 V) ISUP 22 µA 14 V < VSUP ≤ 36 V, EN = 0 V, TXD and RXD floating 6
Under voltage VSUP threshold, ramp up UVSUP(R) 4.15 4.45 V Ramp up 6
Under voltage VSUP threshold, ramp down UVSUP(F) 3.5 4 V Ramp down 6
RXD low-level voltage VOL 0.6 V Based upon external pull-up to VCC (4) 7
Low-level output current, open drain IOL 1.5 mA LIN = 0 V, RXD = 0.4 V 7
Leakage current, high-level (RXD) ILKG -5 5 µA LIN = VSUP, RXD = VCC 7
TXD low-level input voltage VIL 0.8 V 7
TXD high-level input voltage VIH 2 V 7
TXD low-level input leakage current ILKG -5 5 µA TXD = 0 V 7
TXD internal pull-down resistor value RTXD 125 350 800 kΩ 7
EN low-level input voltage VIL -0.3 0.8 V 7
EN high-level input voltage VIH 2 5.25 V 7
EN hysteresis voltage VHYS 30 500 mV By design and characterization 7
EN low-level input current IIL -5 5 µA EN = 0 V 7
EN internal pull-down resistor REN 125 350 800 kΩ 7
LIN recessive high-level output voltage VOH 0.85 VSUP TXD = VCC, IO = 0 mA; 7 V ≤ VSUP ≤ 36 V 7
LIN recessive high-level output voltage VOH 3 V TXD = VCC, IO = 0 mA; 4.5 V ≤ VSUP < 7 V 7
LIN dominant low-level output voltage VOL 0.2 VSUP TXD = 0 V; 7 V ≤ VSUP ≤ 36 V 7
LIN dominant low-level output voltage VOL 1.2 V TXD = 0 V; 4.5 V ≤ VSUP < 7 V 7
Low-level input voltage (ISO 17987 Param 17) VBUSdom 0.4 VSUP LIN dominant (including LIN dominant for wake up); See 图 8-3 and 图 8-4 7
High-level input voltage (ISO 17987 Param 18) VBUSrec 0.6 VSUP LIN recessive; See 图 8-3 and 图 8-4 7
LIN recessive high-level input voltage threshold VIH 0.47 0.6 VSUP 7 V ≤ VSUP ≤ 18 V 7
LIN dominant low-level input voltage threshold VIL 0.4 0.53 VSUP 7 V ≤ VSUP ≤ 18 V 7
Receiver center threshold VBUS_CNT 0.475 0.5 0.525 VSUP VBUS_CNT = (VBUSrec + VBUSdom)/2; See 图 8-3 and 图 8-4 7
Hysteresis voltage (SAE J2602) VHYS 0.07 0.175 VSUP VHYS = VIH - VIL; See 图 8-3 and 图 8-4 7
Serial diode LIN termination pull-up path VSERIAL_DIODE 0.4 0.7 1 V ISERIAL_DIODE = 10 µA 7
Limiting current (ISO 17987 Param 12) IBUS(LIM) 40 90 200 mA TXD = 0 V, VLIN = 18 V, VSUP = 18 V 7
Receiver leakage current, dominant IBUS_PAS_dom -1 mA Driver off/recessive, LIN = 0 V, VSUP = 12 V; See 图 8-6 7
Receiver leakage current, recessive (LIN ≥ VSUP) IBUS_PAS_rec1 20 µA Driver off/recessive, LIN ≥ VSUP, 4.5 V ≤ VSUP ≤ 36 V; See 图 8-7 7
Pull-up current source to VSUP, sleep mode IRSLEEP -20 -1.5 µA VSUP = 14 V, LIN = GND 8
Pull-up resistor to VSUP RPU 20 45 60 kΩ Normal and standby modes 8
Leakage current, loss of ground (LIN dominant) Ileak gnd(dom) -1 1 mA VSUP = 8 V, GND = open, VSUP = 18 V, GND = open; RCOMMANDER = 1 kΩ, CL = 1 nF; RRESPONDER = 20 kΩ, CL = 1 nF; LIN = dominant 8
Receiver rising propagation delay time trx_pdr 5 µs ISO 17987 Param 31; 5.5 V ≤ VSUP, RRXD = 2.4 kΩ, CRXD = 20 pF; See 图 8-12 and 图 8-13 10
Receiver falling propagation delay time trx_pdf 5 µs ISO 17987 Param 31 10
Symmetry of receiver propagation delay time (trx_sym = trx_pdf, trx_pdr) trx_sym -2 2 µs ISO 17987 Param 32; RRXD = 2.4 kΩ, CRXD = 20 pF; See 图 8-12 and 图 8-13 10
Minimum dominant time on LIN bus for wake-up tLINBUS 25 65 150 µs See 图 8-16, 图 9-2 and 图 9-3 10
Time to clear false wake-up prevention logic (recessive time to clear bus stuck dominant) tCLEAR 8 25 50 µs See 图 9-3 10
Mode change delay time (normal to sleep through EN pin) tMODE_CHANGE 2 15 µs See 图 9-4 and 图 8-14 10
Normal mode initialization time tNOMINT 45 µs See 图 8-14 10
Power-up time tPWR 1.5 ms Time it takes for valid data on RXD upon power-up 10
Dominant state time out tTXD_DTO 20 50 80 ms 10

CAD (KiCad official)

  • Symbol: TLIN1039DDFRQ1
  • Footprint: Package_TO_SOT_SMD:TSOT-23-8
  • 3D model: TSOT-23-8 (KiCad packages3D, STEP)
  • 3D model files: tlin1039ddfrq1-etched.step / tlin1039ddfrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlin1039ddfrq1.step / tlin1039ddfrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 ca856e5d1ade459a, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF