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TLF11251EPXUMA1
Public Made by Adomby adom
Infineon Technologies Pre-ordered Chips, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLF11251EPXUMA1
Infineon Technologies · Pre-ordered Chips · HTSSOP-14-EP
TLF11251EPXUMA1 from Infineon Technologies, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Not connected internally; leave it open. |
| 2 | SW | passive | Switch node connected to the half bridge drains, typically the input of the LC filter in buck circuits (pins 2 and 3 are both SW). |
| 3 | SW | passive | Switch node connected to the half bridge drains, typically the input of the LC filter in buck circuits (pins 2 and 3 are both SW). |
| 4 | PGND | power_in | Power ground connected to the half bridge low side source. |
| 5 | GND | power_in | Logical ground. |
| 6 | LSCON | input | Bridge control input defining the low side state during PWM high; high enables synchronous high/low side control, low disables low side control (abs max -0.3 V to 7.0 V). |
| 7 | NC | unconnected | Not connected internally; leave it open. |
| 8 | PWM | input | Control input for the half bridge: high turns the high side off and the low side on, low turns the high side on and the low side off (abs max -0.3 V to 7.0 V, weak internal pull-up). |
| 9 | VCC | power_in | Supply voltage input for the PWM and LSCON inputs, functional range 2.35 V to 7.0 V. |
| 10 | PGND | power_in | Power ground connected to the half bridge low side source. |
| 11 | NC | unconnected | Not connected internally; leave it open. |
| 12 | VS | power_in | Supply to the gate drivers connected to the half bridge high side source, functional range 3.5 V to 7.0 V. |
| 13 | VS | power_in | Supply to the gate drivers connected to the half bridge high side source, functional range 3.5 V to 7.0 V. |
| 14 | NC | unconnected | Not connected internally; leave it open. |
| 15 | Heat sink | passive | Exposed heat sink pad; connect to the heat sink area and to GND and PGND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | HTSSOP-14-EP |
| Category | Interface ICs |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Propagation time, PWM falling edge | tprop,fe | 60 | ns | High side drain connected to resistive load; VCC > 3.0 V; VS > 4.5 V | 14 | ||
| Propagation time, PWM rising edge | tprop,re | 60 | ns | Low side drain connected to resistive load; VCC > 3.0 V; VS > 4.5 V | 14 | ||
| Minimum pulse width input | tpulse,min | 65 | ns | 14 | |||
| Pulse resolution time | tres | 3 | ns | 14 | |||
| LSCON frequency detector frequency range | fdet,lscon | 0.72 | MHz | 14 | |||
| LSCON frequency detector filter time | tfil,lscon | 3 | µs | 14 | |||
| Input voltage high | VIH | 0.67 | V | CMOS function; min is 0.67 × Vcc | 14 | ||
| Input voltage low | VIL | 0.33 | V | CMOS function; max is 0.33 × Vcc | 14 | ||
| Input voltage hysteresis | VIHYS | 0.05 | V | 14 | |||
| On-state resistance high side | RONHS | 100 | mΩ | Tj ≤ 150°C; Id = -2 A; Vs = 5.8 V | 15 | ||
| On-state resistance high side | RONHS | 70 | mΩ | Tj ≤ 85°C; Id = -2 A; Vs = 5.8 V | 15 | ||
| On-state resistance low side | RONLS | 105 | mΩ | Tj ≤ 150°C; Id = 2 A; Vs = 5.8 V | 15 | ||
| On-state resistance low side | RONLS | 75 | mΩ | Tj ≤ 85°C; Id = 2 A; Vs = 5.8 V | 15 | ||
| Body diode forward voltage high side | VDFHS | 0.67 | 0.95 | V | Ifw = 2 A | 15 | |
| Body diode forward voltage low side | VDFLS | 0.72 | 0.91 | V | Ifw = 2 A | 15 | |
| Undervoltage limit at VCC supply | Vccuv | 1.95 | 2.28 | V | VCC falling | 17 | |
| Undervoltage detector hysteresis | Vccuvh | 0.05 | 0.1 | V | 17 | ||
| Undervoltage detector reaction time | Vuvr | 3 | µs | 17 | |||
| Overcurrent sensing limit | Ioc, lim | -4.4 | -2.6 | A | 19 | ||
| Startup protection inactive, number of PWM pulses | npwm,st | 5500 | VCC rising above VCC,min | 19 | |||
| Overtemperature shutdown | TjOT | 175 | 200 | °C | 20 | ||
| Switch-on temperature | TjSO | 165 | °C | 20 | |||
| Overtemperature switch-on hysteresis | dTj | 15 | °C | 20 | |||
| Supply voltage VS | VS | -0.3 | 7 | V | 8 | ||
| Supply voltage VCC | Vcc | -0.3 | 7 | V | 8 | ||
| Switch node SW | VSW | -0.3 | 7 | V | 8 | ||
| Input PWM | VPWM | -0.3 | 7 | V | 8 | ||
| Input LSCON | VLSCON | -0.3 | 7 | V | 8 | ||
| Continuous drain current high side | IDHS | -2.5 | A | PWM = off | 8 | ||
| Continuous drain current low side | IDLS | 2.5 | A | PWM = on | 8 | ||
| Pulsed drain current high side | IDHS | -4.4 | A | Valid during active overcurrent protection | 8 | ||
| Pulsed drain current low side | IDLS | 4.4 | A | Valid during active overcurrent protection | 8 | ||
| Junction temperature | Tj | -40 | 150 | °C | 8 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 8 | ||
| ESD susceptibility all pins | VESD | -2 | 2 | kV | HBM | 8 | |
| ESD susceptibility all pins | VESD | -500 | 500 | V | CDM | 8 | |
| ESD susceptibility (corner pins) | VESD | -750 | 750 | V | CDM | 8 | |
| Supply voltage range VS | VS,nom | 3.5 | 7 | V | 9 | ||
| Supply voltage range VCC | VCC,nom | 2.35 | 7 | V | 9 | ||
| Supply voltage VS transient slew rate | dVS/dt | -120 | 120 | V/ms | 9 | ||
| Supply voltage VCC transient slew rate | dVCC/dt | -120 | 120 | V/ms | 9 | ||
| Junction temperature | Tj | -40 | 175 | °C | 9 | ||
| Supply current total, normal operation | IC,norm | 35 | mA | PWM input @ 1.8 MHz | 9 | ||
| Supply current total, no switching | IC,ns | 200 | µA | VS < 5.8 V; Vcc < 5.1 V; Tj < 85°C | 9 | ||
| Junction to case top, high side | RthJCT(HS) | 30.9 | 34.1 | K/W | 10 | ||
| Junction to case top, low side | RthJCT(LS) | 39.5 | 43.7 | K/W | 10 | ||
| Junction to case bottom, high side | RthJCB(HS) | 9.6 | 10.6 | K/W | 10 | ||
| Junction to case bottom, low side | RthJCB(LS) | 13.4 | 14.8 | K/W | 10 | ||
| Junction to ambient | RthJA | 43.3 | K/W | JEDEC JESD51-2,-5,-7 natural convection, FR4 2s2p board | 10 | ||
| Dead time high to low | tdead,hl | 15 | ns | 14 | |||
| Dead time low to high | tdead,lh | 18 | ns | 14 | |||
| Input capacitance | CIN | 10 | pF | 14 |
CAD (KiCad official)
- Symbol:
TLF11251EPXUMA1 - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
- 3D model files:
tlf11251epxuma1-etched.step/tlf11251epxuma1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlf11251epxuma1.step/tlf11251epxuma1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (25 pp, sha256
21b7688634656c63, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).