TLE9842-2QX

Infineon Technologies · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

TLE9842-2QX from Infineon Technologies, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LIN	bidirectional	LIN bus interface input/output of the integrated LIN 2.2 transceiver, with pull-up enabled after reset.
2	GNDLIN	power_in	LIN ground.
3	HS1	output	High-side switch output 1, Hi-Z after reset; can be cyclically switched in cyclic sense mode and used for PWM.
4	HS2	output	High-side switch output 2, Hi-Z after reset; can be cyclically switched in cyclic sense mode and used for PWM.
5	MON1	input	High voltage monitor input 1 for wake-up and cyclic sense.
6	MON2	input	High voltage monitor input 2 for wake-up and cyclic sense.
7	MON3	input	High voltage monitor input 3 for wake-up and cyclic sense.
8	MON4	input	High voltage monitor input 4 for wake-up and cyclic sense.
9	MON5	input	High voltage monitor input 5 for wake-up and cyclic sense.
10	N.C.	unconnected	Not connected, can be connected to GND.
11	LS1	output	Low-side switch output 1, Hi-Z after reset.
12	LS2	output	Low-side switch output 2, Hi-Z after reset.
13	GNDLS	power_in	Low-side ground for LS1 and LS2.
14	P1.0	bidirectional	Port 1 general purpose I/O bit 0 with input reset state; alternate functions per Table 9.
15	P1.1	bidirectional	Port 1 general purpose I/O bit 1 with input reset state; alternate functions per Table 9.
16	P1.2	bidirectional	Port 1 general purpose I/O bit 2 with input reset state; alternate functions per Table 9.
17	P0.1	bidirectional	Port 0 general purpose I/O bit 1 with pull-up enabled after reset; alternate functions per Table 8.
18	TMS / SWD_IO	bidirectional	Test mode select input (TMS) with pull-down after reset, also used as Serial Wire Debug input/output (SWD_IO).
19	GNDP	power_in	Core supply ground.
20	P0.0 / SWD_CLK	bidirectional	Port 0 general purpose I/O bit 0 with pull-up enabled after reset, also used as Serial Wire Debug clock (SWD_CLK).
21	RESET	bidirectional	Reset input/output with pull-up, not available during Sleep Mode.
22	P0.2	bidirectional	Port 0 general purpose I/O bit 2 with pull-down enabled after reset; alternate functions per Table 8.
23	P0.3	bidirectional	Port 0 general purpose I/O bit 3 with pull-up enabled after reset; alternate functions per Table 8.
24	P0.4	bidirectional	Port 0 general purpose I/O bit 4 with pull-up enabled after reset; alternate functions per Table 8.
25	P0.5	bidirectional	Port 0 general purpose I/O bit 5 with pull-up enabled after reset; alternate functions per Table 8.
26	P1.4	bidirectional	Port 1 general purpose I/O bit 4 with input reset state; alternate functions per Table 9.
27	N.C.	unconnected	Not connected, can be connected to GND.
28	N.C.	unconnected	Not connected, can be connected to GND.
29	N.C.	unconnected	Not connected, can be connected to GND.
30	GNDP	power_in	Core supply ground.
31	P2.5 / XTAL2	output	Port 2 bit 5 (input-only port) used as external oscillator output XTAL2, Hi-Z after reset.
32	P2.4 / XTAL1	input	Port 2 bit 4 (input-only port) used as external oscillator input XTAL1.
33	P2.2	input	Port 2 bit 2, input-only; ADC1 analog input channel 8 (AN2).
34	P2.6	input	Port 2 bit 6, input-only; ADC1 analog input channel 10 (AN6).
35	P2.7	input	Port 2 bit 7, input-only; ADC1 analog input channel 11 (AN7).
36	P2.3	input	Port 2 bit 3, input-only; ADC1 analog input channel 9 (AN3).
37	P2.1	input	Port 2 bit 1, input-only; ADC1 analog input channel 7 (AN1).
38	N.C.	unconnected	Not connected, can be connected to GND.
39	P2.0	input	Port 2 bit 0, input-only; ADC1 analog input channel 12 (AN0).
40	N.C.	unconnected	Not connected, can be connected to GND.
41	N.C.	unconnected	Not connected, can be connected to GND.
42	VDDC	power_out	Core supply, 1.5 V in Active Mode and 0.9 V in Stop Mode; do not connect external loads, only buffer/bypass capacitor.
43	GNDA	power_in	Analog supply ground.
44	VDDP	power_out	I/O port supply, 5.0 V; do not connect external loads, only buffer and bypass capacitors.
45	VDDEXT	power_out	External voltage supply output, 5.0 V, 20 mA, for external loads such as Hall sensors.
46	N.C.	unconnected	Not connected, can be connected to GND.
47	VS	power_in	Battery supply input; single supply range 3.0 V to 28 V.
48	VBAT_SENSE	input	Battery supply voltage sense input.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	VQFN-48-EP(7x7)
Category	Embedded Processors & Controllers
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VS voltage (absolute maximum)	VS,max	-0.3		40	V	Load dump	86
VDDP voltage (absolute maximum)	VDDP,max	-0.3		5.5	V		86
VDDEXT voltage (absolute maximum)	VDDEXT,max	-0.3			V		86
VDDC voltage (absolute maximum)	VDDC,max	-0.3		1.6	V		86
Voltage at VBAT_SENSE pin (absolute maximum)	VBAT_SENSE,max	-28		40	V		86
Voltage at HS pin (absolute maximum)	VHS,max	-0.3			V		86
Voltage at LIN pin (absolute maximum)	VLIN,max	-28		40	V		86
Voltage at MON_x pins (absolute maximum)	VMON,max	-28		40	V		86
Voltage at LS pin (absolute maximum)	VLS,max	-0.3		40	V	Internal clamping structure > 40V	86
Voltage on port pin P0.x, P1.x, P2.x, TMS, RESET (absolute maximum)	VIO,max	-0.3			V	VIN < VDDPmax	86
Injection current on P0.x, P1.x, P2.x, TMS, RESET in Sleep Mode	Ixx			5	mA	Maximum allowed injection current on single pin or sum of pins in Sleep Mode and unpowered device	86
Injection current on HS	IXLO			150	mA	Current flowing into HS pin (back supply in case of short to battery)	86
Output current on LS	ILS	-300			mA	Current flowing out of LS pin, e.g. reverse polarity event (defined in LV124) or ISO Pulse event (defined in ISO 7637-2)	87
Junction temperature (absolute maximum)	Tj	-40		150	°C		87
Storage temperature	Tstg	-55		150	°C		87
ESD susceptibility HBM, all pins	VESD1	-2		2	kV	JEDEC HBM	87
ESD susceptibility HBM, LIN vs. LINGND	VESD3	-6		6	kV	Pins LIN vs. LINGND; JEDEC HBM	87
ESD susceptibility CDM	VESD_CDM	-500		500	V	Charged device model, acc. JEDEC JESD22-C101	87
Supply voltage in Active Mode	VS_AM	5.5		28	V		88
Extended supply voltage in Active Mode - Range 1	VS_AM_extend_1	28		40	V	Functional with parameter deviation	88
Extended supply voltage in Active Mode with reduced functionality - Range 2	VS_AM_extend_2	3		5.5	V	Functional with parameter deviation	88
Specified supply voltage for LIN transceiver - Active Mode	VS_AM_LIN	5.5		18	V	Parameter specification	88
Extended supply voltage for LIN transceiver - Active Mode	VS_AM_LIN_extend	4.8		28	V	Functional with parameter deviation	88
Extended supply voltage for LIN & Monitoring Input (MON) - Stop & Sleep Mode	VS_SSM_LIN_MON_extend	3.6		5.5	V	Wakeup functionality ensured	88
Minimum supply voltage in Stop Mode	VS_Stopmin	3			V		88
Minimum supply voltage in Sleep Mode	VS_Sleepmin	3			V		88
Supply voltage transients slew rate	dVS/dt	-5		5	V/µs		88
Output current on any GPIO	IOH, IOL	-10		10	mA		88
Output sum current for all GPIO pins	IGPIO,sum	-50		50	mA		88
Operating frequency	fsys	5		40	MHz		88
Junction temperature (functional range)	Tj	-40		150	°C		88
Current consumption in Active Mode	IVs		19	22	mA	fsys = 40 MHz; Vs = 5.5V to 28V; all digital modules enabled, ADCs converting in sequencer mode, PLL running, no loads on GPIOs, VDDEXT off, LIN recessive, HSx & LSx enabled but off	89
Current consumption in Active Mode (reduced frequency)	IVs_freduced			15	mA	fsys = 10 MHz; Vs = 13.5V; all digital modules enabled, ADCs converting in sequencer mode, PLL running, no loads on GPIOs, VDDEXT off, LIN recessive, HSx & LSx enabled but off	89
Current consumption in Sleep Mode	ISleep			15	µA	TJ = -40°C to 25°C; Vs = 13.5V; wake capable via LIN and MON	89
Current consumption in Sleep Mode (extended temperature range)	ISleep(T_extend)			25	µA	TJ = 25°C to 85°C; Vs = 13.5V; wake capable via LIN and MON	89
Current consumption in Sleep Mode (extended voltage and temperature range)	ISleep(V_T_extend)			30	µA	TJ = -40°C to 85°C; Vs = 5.5V to 18V; wake capable via LIN and MON	89
Current consumption in Sleep Mode (extended voltage and temperature range 2)	ISleep(V_T_extend2)			40	µA	TJ = -40°C to 85°C; Vs = 3V to 28V; wake capable via LIN and MON	90
Current consumption in Sleep Mode with cyclic wake	ICyclic			15	µA	TJ = -40°C to 25°C; Vs = 13.5V; during sleep period	90
Current consumption in Sleep Mode with cyclic wake (extended temperature range)	ICyclic(T_extend)			30	µA	TJ = 25°C to 85°C; Vs = 13.5V; during sleep period	90
Current consumption in Stop Mode	IStop		65	115	µA	System in Stop Mode, microcontroller not clocked, wake capable via LIN and MON; GPIOs open or to GND; TJ = -40°C to 85°C	90
Current consumption in Stop Mode (extended voltage)	IStop_V_extend		3.5	4	mA	System in Stop Mode, microcontroller not clocked, wake capable via LIN and MON; GPIOs open or to GND; TJ = -40°C to 85°C; Vs = 3V	90
Current consumption in Stop Mode with cyclic sense	IStop_CS		70	125	µA	System in Stop Mode (during stop period), microcontroller not clocked; VDDEXT off; High Side off; GPIOs open, GND or VDDP; TJ = -40°C to 85°C; Vs = 5.5V to 28V	90
Thermal resistance junction to case	Rth(JC)		6		K/W	Measured to exposed pad; not subject to production test	91
Thermal resistance junction to ambient	Rth(JA)		33		K/W	JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board	91
Wake-up over battery	tstart			1	ms	Battery ramp-up till MCU reset is released; Vs > 3V and RESET = '1'	91
Sleep-exit time	tsleep-exit			1	ms	Rising/falling edge of any wake-up signal (LIN, MON) till MCU software running	91
Sleep-entry time	tsleep-entry			330	µs		91
Required decoupling capacitance on VS	CVS1	0.1			µF	ESR < 1Ω	92
Required buffer capacitance for stability on VS (load jumps)	CVS2	10			µF		92
Specified output current VDDP	IVDDP	0		50	mA		92
Required decoupling capacitance on VDDP	CVDDP1	0.47			µF	ESR < 1Ω	92
Output voltage VDDP including line and load regulation - Active Mode	VDDPOUT	4.9	5	5.1	V	Iload < 90mA; Vs > 5.5V	92
Output voltage VDDP including line and load regulation - Stop Mode	VDDPOUTSTOP	4.5	5	5.25	V	Iload is only internal; Vs > 5.5V	92
Over voltage detection VDDP	VDDPOV	5.14		5.4	V	Vs > 5.5V; overvoltage leads to SUPPLY_NMI	92
Under voltage reset VDDP	VDDPUV	2.55	2.7	2.8	V		93
Required decoupling capacitance on VDDC	CVDDC1	0.1			µF	ESR < 1Ω	94
Output voltage VDDC including line regulation - Active Mode/Stop Mode	VDDCOUT	1.44	1.5	1.56	V	Iload < 40mA; with setting of VDDC output voltage to 1.5V in Stop Mode	94
Over voltage detection VDDC	VDDCOV	1.58		1.68	V	Overvoltage leads to SUPPLY_NMI	94
Digital core supply voltage	VDDC	1.35		1.6	V	Full active mode	107
Digital supply voltage for IO pads	VDDP	2.55	5	5.5	V		107

CAD (KiCad official)

Symbol: TLE9842-2QX
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: tle9842-2qx-etched.step / tle9842-2qx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle9842-2qx.step / tle9842-2qx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (128 pp, sha256 52387b2e16d19421, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TLE9842-2QX

**Infineon Technologies** · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

TLE9842-2QX from Infineon Technologies, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LIN | bidirectional | LIN bus interface input/output of the integrated LIN 2.2 transceiver, with pull-up enabled after reset. |
| 2 | GNDLIN | power_in | LIN ground. |
| 3 | HS1 | output | High-side switch output 1, Hi-Z after reset; can be cyclically switched in cyclic sense mode and used for PWM. |
| 4 | HS2 | output | High-side switch output 2, Hi-Z after reset; can be cyclically switched in cyclic sense mode and used for PWM. |
| 5 | MON1 | input | High voltage monitor input 1 for wake-up and cyclic sense. |
| 6 | MON2 | input | High voltage monitor input 2 for wake-up and cyclic sense. |
| 7 | MON3 | input | High voltage monitor input 3 for wake-up and cyclic sense. |
| 8 | MON4 | input | High voltage monitor input 4 for wake-up and cyclic sense. |
| 9 | MON5 | input | High voltage monitor input 5 for wake-up and cyclic sense. |
| 10 | N.C. | unconnected | Not connected, can be connected to GND. |
| 11 | LS1 | output | Low-side switch output 1, Hi-Z after reset. |
| 12 | LS2 | output | Low-side switch output 2, Hi-Z after reset. |
| 13 | GNDLS | power_in | Low-side ground for LS1 and LS2. |
| 14 | P1.0 | bidirectional | Port 1 general purpose I/O bit 0 with input reset state; alternate functions per Table 9. |
| 15 | P1.1 | bidirectional | Port 1 general purpose I/O bit 1 with input reset state; alternate functions per Table 9. |
| 16 | P1.2 | bidirectional | Port 1 general purpose I/O bit 2 with input reset state; alternate functions per Table 9. |
| 17 | P0.1 | bidirectional | Port 0 general purpose I/O bit 1 with pull-up enabled after reset; alternate functions per Table 8. |
| 18 | TMS / SWD_IO | bidirectional | Test mode select input (TMS) with pull-down after reset, also used as Serial Wire Debug input/output (SWD_IO). |
| 19 | GNDP | power_in | Core supply ground. |
| 20 | P0.0 / SWD_CLK | bidirectional | Port 0 general purpose I/O bit 0 with pull-up enabled after reset, also used as Serial Wire Debug clock (SWD_CLK). |
| 21 | RESET | bidirectional | Reset input/output with pull-up, not available during Sleep Mode. |
| 22 | P0.2 | bidirectional | Port 0 general purpose I/O bit 2 with pull-down enabled after reset; alternate functions per Table 8. |
| 23 | P0.3 | bidirectional | Port 0 general purpose I/O bit 3 with pull-up enabled after reset; alternate functions per Table 8. |
| 24 | P0.4 | bidirectional | Port 0 general purpose I/O bit 4 with pull-up enabled after reset; alternate functions per Table 8. |
| 25 | P0.5 | bidirectional | Port 0 general purpose I/O bit 5 with pull-up enabled after reset; alternate functions per Table 8. |
| 26 | P1.4 | bidirectional | Port 1 general purpose I/O bit 4 with input reset state; alternate functions per Table 9. |
| 27 | N.C. | unconnected | Not connected, can be connected to GND. |
| 28 | N.C. | unconnected | Not connected, can be connected to GND. |
| 29 | N.C. | unconnected | Not connected, can be connected to GND. |
| 30 | GNDP | power_in | Core supply ground. |
| 31 | P2.5 / XTAL2 | output | Port 2 bit 5 (input-only port) used as external oscillator output XTAL2, Hi-Z after reset. |
| 32 | P2.4 / XTAL1 | input | Port 2 bit 4 (input-only port) used as external oscillator input XTAL1. |
| 33 | P2.2 | input | Port 2 bit 2, input-only; ADC1 analog input channel 8 (AN2). |
| 34 | P2.6 | input | Port 2 bit 6, input-only; ADC1 analog input channel 10 (AN6). |
| 35 | P2.7 | input | Port 2 bit 7, input-only; ADC1 analog input channel 11 (AN7). |
| 36 | P2.3 | input | Port 2 bit 3, input-only; ADC1 analog input channel 9 (AN3). |
| 37 | P2.1 | input | Port 2 bit 1, input-only; ADC1 analog input channel 7 (AN1). |
| 38 | N.C. | unconnected | Not connected, can be connected to GND. |
| 39 | P2.0 | input | Port 2 bit 0, input-only; ADC1 analog input channel 12 (AN0). |
| 40 | N.C. | unconnected | Not connected, can be connected to GND. |
| 41 | N.C. | unconnected | Not connected, can be connected to GND. |
| 42 | VDDC | power_out | Core supply, 1.5 V in Active Mode and 0.9 V in Stop Mode; do not connect external loads, only buffer/bypass capacitor. |
| 43 | GNDA | power_in | Analog supply ground. |
| 44 | VDDP | power_out | I/O port supply, 5.0 V; do not connect external loads, only buffer and bypass capacitors. |
| 45 | VDDEXT | power_out | External voltage supply output, 5.0 V, 20 mA, for external loads such as Hall sensors. |
| 46 | N.C. | unconnected | Not connected, can be connected to GND. |
| 47 | VS | power_in | Battery supply input; single supply range 3.0 V to 28 V. |
| 48 | VBAT_SENSE | input | Battery supply voltage sense input. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | VQFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VS voltage (absolute maximum) | VS,max | -0.3 |  | 40 | V | Load dump | 86 |
| VDDP voltage (absolute maximum) | VDDP,max | -0.3 |  | 5.5 | V |  | 86 |
| VDDEXT voltage (absolute maximum) | VDDEXT,max | -0.3 |  |  | V |  | 86 |
| VDDC voltage (absolute maximum) | VDDC,max | -0.3 |  | 1.6 | V |  | 86 |
| Voltage at VBAT_SENSE pin (absolute maximum) | VBAT_SENSE,max | -28 |  | 40 | V |  | 86 |
| Voltage at HS pin (absolute maximum) | VHS,max | -0.3 |  |  | V |  | 86 |
| Voltage at LIN pin (absolute maximum) | VLIN,max | -28 |  | 40 | V |  | 86 |
| Voltage at MON_x pins (absolute maximum) | VMON,max | -28 |  | 40 | V |  | 86 |
| Voltage at LS pin (absolute maximum) | VLS,max | -0.3 |  | 40 | V | Internal clamping structure > 40V | 86 |
| Voltage on port pin P0.x, P1.x, P2.x, TMS, RESET (absolute maximum) | VIO,max | -0.3 |  |  | V | VIN < VDDPmax | 86 |
| Injection current on P0.x, P1.x, P2.x, TMS, RESET in Sleep Mode | Ixx |  |  | 5 | mA | Maximum allowed injection current on single pin or sum of pins in Sleep Mode and unpowered device | 86 |
| Injection current on HS | IXLO |  |  | 150 | mA | Current flowing into HS pin (back supply in case of short to battery) | 86 |
| Output current on LS | ILS | -300 |  |  | mA | Current flowing out of LS pin, e.g. reverse polarity event (defined in LV124) or ISO Pulse event (defined in ISO 7637-2) | 87 |
| Junction temperature (absolute maximum) | Tj | -40 |  | 150 | °C |  | 87 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 87 |
| ESD susceptibility HBM, all pins | VESD1 | -2 |  | 2 | kV | JEDEC HBM | 87 |
| ESD susceptibility HBM, LIN vs. LINGND | VESD3 | -6 |  | 6 | kV | Pins LIN vs. LINGND; JEDEC HBM | 87 |
| ESD susceptibility CDM | VESD_CDM | -500 |  | 500 | V | Charged device model, acc. JEDEC JESD22-C101 | 87 |
| Supply voltage in Active Mode | VS_AM | 5.5 |  | 28 | V |  | 88 |
| Extended supply voltage in Active Mode - Range 1 | VS_AM_extend_1 | 28 |  | 40 | V | Functional with parameter deviation | 88 |
| Extended supply voltage in Active Mode with reduced functionality - Range 2 | VS_AM_extend_2 | 3 |  | 5.5 | V | Functional with parameter deviation | 88 |
| Specified supply voltage for LIN transceiver - Active Mode | VS_AM_LIN | 5.5 |  | 18 | V | Parameter specification | 88 |
| Extended supply voltage for LIN transceiver - Active Mode | VS_AM_LIN_extend | 4.8 |  | 28 | V | Functional with parameter deviation | 88 |
| Extended supply voltage for LIN & Monitoring Input (MON) - Stop & Sleep Mode | VS_SSM_LIN_MON_extend | 3.6 |  | 5.5 | V | Wakeup functionality ensured | 88 |
| Minimum supply voltage in Stop Mode | VS_Stopmin | 3 |  |  | V |  | 88 |
| Minimum supply voltage in Sleep Mode | VS_Sleepmin | 3 |  |  | V |  | 88 |
| Supply voltage transients slew rate | dVS/dt | -5 |  | 5 | V/µs |  | 88 |
| Output current on any GPIO | IOH, IOL | -10 |  | 10 | mA |  | 88 |
| Output sum current for all GPIO pins | IGPIO,sum | -50 |  | 50 | mA |  | 88 |
| Operating frequency | fsys | 5 |  | 40 | MHz |  | 88 |
| Junction temperature (functional range) | Tj | -40 |  | 150 | °C |  | 88 |
| Current consumption in Active Mode | IVs |  | 19 | 22 | mA | fsys = 40 MHz; Vs = 5.5V to 28V; all digital modules enabled, ADCs converting in sequencer mode, PLL running, no loads on GPIOs, VDDEXT off, LIN recessive, HSx & LSx enabled but off | 89 |
| Current consumption in Active Mode (reduced frequency) | IVs_freduced |  |  | 15 | mA | fsys = 10 MHz; Vs = 13.5V; all digital modules enabled, ADCs converting in sequencer mode, PLL running, no loads on GPIOs, VDDEXT off, LIN recessive, HSx & LSx enabled but off | 89 |
| Current consumption in Sleep Mode | ISleep |  |  | 15 | µA | TJ = -40°C to 25°C; Vs = 13.5V; wake capable via LIN and MON | 89 |
| Current consumption in Sleep Mode (extended temperature range) | ISleep(T_extend) |  |  | 25 | µA | TJ = 25°C to 85°C; Vs = 13.5V; wake capable via LIN and MON | 89 |
| Current consumption in Sleep Mode (extended voltage and temperature range) | ISleep(V_T_extend) |  |  | 30 | µA | TJ = -40°C to 85°C; Vs = 5.5V to 18V; wake capable via LIN and MON | 89 |
| Current consumption in Sleep Mode (extended voltage and temperature range 2) | ISleep(V_T_extend2) |  |  | 40 | µA | TJ = -40°C to 85°C; Vs = 3V to 28V; wake capable via LIN and MON | 90 |
| Current consumption in Sleep Mode with cyclic wake | ICyclic |  |  | 15 | µA | TJ = -40°C to 25°C; Vs = 13.5V; during sleep period | 90 |
| Current consumption in Sleep Mode with cyclic wake (extended temperature range) | ICyclic(T_extend) |  |  | 30 | µA | TJ = 25°C to 85°C; Vs = 13.5V; during sleep period | 90 |
| Current consumption in Stop Mode | IStop |  | 65 | 115 | µA | System in Stop Mode, microcontroller not clocked, wake capable via LIN and MON; GPIOs open or to GND; TJ = -40°C to 85°C | 90 |
| Current consumption in Stop Mode (extended voltage) | IStop_V_extend |  | 3.5 | 4 | mA | System in Stop Mode, microcontroller not clocked, wake capable via LIN and MON; GPIOs open or to GND; TJ = -40°C to 85°C; Vs = 3V | 90 |
| Current consumption in Stop Mode with cyclic sense | IStop_CS |  | 70 | 125 | µA | System in Stop Mode (during stop period), microcontroller not clocked; VDDEXT off; High Side off; GPIOs open, GND or VDDP; TJ = -40°C to 85°C; Vs = 5.5V to 28V | 90 |
| Thermal resistance junction to case | Rth(JC) |  | 6 |  | K/W | Measured to exposed pad; not subject to production test | 91 |
| Thermal resistance junction to ambient | Rth(JA) |  | 33 |  | K/W | JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board | 91 |
| Wake-up over battery | tstart |  |  | 1 | ms | Battery ramp-up till MCU reset is released; Vs > 3V and RESET = '1' | 91 |
| Sleep-exit time | tsleep-exit |  |  | 1 | ms | Rising/falling edge of any wake-up signal (LIN, MON) till MCU software running | 91 |
| Sleep-entry time | tsleep-entry |  |  | 330 | µs |  | 91 |
| Required decoupling capacitance on VS | CVS1 | 0.1 |  |  | µF | ESR < 1Ω | 92 |
| Required buffer capacitance for stability on VS (load jumps) | CVS2 | 10 |  |  | µF |  | 92 |
| Specified output current VDDP | IVDDP | 0 |  | 50 | mA |  | 92 |
| Required decoupling capacitance on VDDP | CVDDP1 | 0.47 |  |  | µF | ESR < 1Ω | 92 |
| Output voltage VDDP including line and load regulation - Active Mode | VDDPOUT | 4.9 | 5 | 5.1 | V | Iload < 90mA; Vs > 5.5V | 92 |
| Output voltage VDDP including line and load regulation - Stop Mode | VDDPOUTSTOP | 4.5 | 5 | 5.25 | V | Iload is only internal; Vs > 5.5V | 92 |
| Over voltage detection VDDP | VDDPOV | 5.14 |  | 5.4 | V | Vs > 5.5V; overvoltage leads to SUPPLY_NMI | 92 |
| Under voltage reset VDDP | VDDPUV | 2.55 | 2.7 | 2.8 | V |  | 93 |
| Required decoupling capacitance on VDDC | CVDDC1 | 0.1 |  |  | µF | ESR < 1Ω | 94 |
| Output voltage VDDC including line regulation - Active Mode/Stop Mode | VDDCOUT | 1.44 | 1.5 | 1.56 | V | Iload < 40mA; with setting of VDDC output voltage to 1.5V in Stop Mode | 94 |
| Over voltage detection VDDC | VDDCOV | 1.58 |  | 1.68 | V | Overvoltage leads to SUPPLY_NMI | 94 |
| Digital core supply voltage | VDDC | 1.35 |  | 1.6 | V | Full active mode | 107 |
| Digital supply voltage for IO pads | VDDP | 2.55 | 5 | 5.5 | V |  | 107 |

## CAD (KiCad official)

- Symbol: `TLE9842-2QX`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `tle9842-2qx-etched.step` / `tle9842-2qx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tle9842-2qx.step` / `tle9842-2qx.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588913683171061760) (128 pp, sha256 `52387b2e16d19421`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tle9842-2qx-datasheet.pdf)