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TLE9351VSJXTMA1

Public Made by Adom

by adom

Infineon Technologies CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLE9351VSJXTMA1

Infineon Technologies · CAN ICs · SOIC-8

TLE9351VSJXTMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TxD input Transmit data input with internal pull-up to VIO; a low level drives the bus dominant, and a continuous low longer than tTxD triggers the TxD time-out.
2 GND power_in Ground.
3 VCC power_in Transmitter supply voltage (abs max -0.3 to 6.0 V) with a recommended 1 µF decoupling capacitor to GND; VCC can be turned off in stand-by mode.
4 RxD output Receive data output that is low in the dominant state, limited to ±5 mA output current and VIO+0.3 V max.
5 VIO power_in Digital supply input (abs max -0.3 to 6.0 V) that adapts logic levels to the microcontroller supply and supplies the low-power receiver, with a recommended 100 nF decoupling capacitor to GND.
6 CANL bidirectional CAN bus low level input/output, short circuit proof to GND and supply, with DC voltage range of -40 to 40 V.
7 CANH bidirectional CAN bus high level input/output, short circuit proof to GND and supply, with DC voltage range of -40 to 40 V.
8 STB input Stand-by mode control input with internal pull-up to VIO; low selects normal-operating mode.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Transmitter supply voltage VCC -0.3 6 V 7
Digital supply voltage VIO -0.3 6 V 7
CANH and CANL DC voltage versus GND VCANH -40 40 V 7
Differential voltage between CANH and CANL VCAN_Diff -40 40 V 7
Voltage at digital input pins STB, TxD VMAX_IO -0.3 6 V 7
RxD output current IRxD -5 5 mA 7
Junction temperature Tj -40 150 °C 7
Storage temperature TS -55 150 °C 7
ESD immunity at CANH, CANL versus GND VESD_HBM_CAN -10 10 kV HBM (100 pF via 1.5 kΩ) 7
ESD immunity at all other pins VESD_HBM_ALL -2 2 kV HBM (100 pF via 1.5 kΩ) 7
Transmitter supply voltage (functional range) VCC 4.75 5.25 V 8
Digital supply voltage (functional range) VIO 3 5.5 V 8
Junction temperature (functional range) Tj -40 150 °C 8
Thermal shutdown temperature, rising TJSD 170 180 190 °C temperature falling: minimum 150°C 8
Thermal shutdown hysteresis ∆T 5 10 20 K 8
Thermal resistance junction to ambient PG-DSO-8 RthJA_DSO8 120 K/W JEDEC JESD51-2,-7 natural convection, FR4 2s2p board 8
Current consumption at VCC normal mode recessive ICC_R 1.4 4 mA VTxD = VIO; VSTB = 0 V; VCANH = VCANL = VCC/2 18
Current consumption at VCC normal mode dominant ICC_D 34 48 mA VTxD = VSTB = 0 V 18
Current consumption at VIO normal mode IIO 0.9 1.5 mA VSTB = 0 V; VDiff = 0 V; recessive 18
Current consumption at VCC stand-by mode ICC(STB) 0.005 5 µA VTxD = VSTB = VIO 18
Current consumption at VIO stand-by mode IIO(STB) 7 18 µA VTxD = VSTB = VIO; 0 V < VCC < 5.5 V 18
VCC undervoltage threshold rising edge VCC_UV_R 3.8 4.2 4.65 V see Figure 8 19
VCC undervoltage threshold falling edge VCC_UV_F 3.8 4.2 4.5 V see Figure 8 19
VCC undervoltage filter time tVCC_UV_filter 4 6 10 µs Figure 8 19
VCC undervoltage recovery time tVCC_recovery 7 70 µs see Figure 8 19
VIO undervoltage threshold VIO_UV 2 2.6 3 V 19
VIO delay time power-up tPON 40 280 µs see Figure 5 19
RxD high level output current IRxD_H -2.5 -1 mA VRxD = VIO -0.4 V; VDiff < 0.5 V 20
RxD low level output current IRxD_L 1 2.5 mA VRxD = 0.4 V; VDiff > 0.9 V 20
TxD high level input voltage VTxD_H 0.7 6 V Recessive state; min is 0.7 × VIO 20
TxD low level input voltage VTxD_L -0.3 0.3 V Dominant state; max is 0.3 × VIO 20
TxD internal pull-up resistor RTxD 35 55 70 kΩ 20
TxD input capacitance CTxD 10 pF 20
TxD permanent dominant time-out tTxD 1 2.3 4 ms Normal-operating mode 20
STB high level input voltage VSTB_H 0.7 6 V stand-by mode; min is 0.7 × VIO 20
STB low level input voltage VSTB_L -0.3 0.3 V Normal-operating mode; max is 0.3 × VIO 20
STB internal pull-up resistor RSTB 35 55 70 kΩ 20
STB input capacitance C(STB) 10 pF 20
Differential range dominant normal mode VDiff_D_Range 0.9 8 V -12 V ≤ VCMR ≤ 12 V 21
Differential range recessive normal mode VDiff_R_Range -3 0.5 V -12V ≤ VCMR ≤ 12 V 21
Differential range dominant stand-by mode VDiff_D_STB_Range 1.15 3 8 V -12 V ≤ VCMR ≤ 12 V 21
Differential range recessive stand-by mode VDiff_R_STB_Range -3 0 0.4 V -12 V ≤ VCMR ≤ 12 V 21
Common mode range CMR -12 12 V 21
Single ended internal resistance RCAN_H, RCAN_L 6 40 50 kΩ recessive state; -2 V ≤ VCANH ≤ 7 V; -2 V ≤ VCANL ≤ 7V 21
Differential internal resistance RDiff 12 80 100 kΩ recessive state; -2 V ≤ VCANH ≤ 7 V; -2 V ≤ VCANL ≤ 7V 21
Input resistance deviation between CANH and CANL ∆Ri -3 3 % recessive state; VCANH = VCANL = 5 V 21
Input capacitance CANH, CANL versus GND CIn 40 pF recessive state; normal-operating mode 21
Differential input capacitance CInDiff 4 20 pF recessive state; normal-operating mode 21
CANL, CANH recessive output voltage normal mode VCANL,H 2 2.5 3 V VTxD = VIO; no load 22
Recessive output voltage difference normal mode VDiff_R_NM -500 -10 50 mV VTxD = VIO; no load 22
CANL dominant output voltage VCANL 0.5 1.5 2.25 V VTxD = 0 V; 50 Ω < RL < 65 Ω 22
CANH dominant output voltage VCANH 2.75 3.4 4.5 V VTxD = 0 V; 50 Ω < RL < 65 Ω 22
Differential voltage dominant normal mode VDiff_D_NM 1.5 1.9 2.5 V VTxD = 0 V; 50 Ω < RL < 65 Ω 22
Differential voltage dominant extended bus load VDiff_EXT_BL 1.4 1.9 3.3 V VTxD = 0 V; 45 Ω < RL < 70 Ω 22
Differential voltage dominant high extended bus load VDiff_HEXT_BL 1.5 3.5 5 V VTxD = 0 V; RL = 2240Ω; static behavior 22
Recessive output voltage difference stand-by mode VDiff_STB -0.2 0.001 0.2 V No load 22
Recessive output voltage stand-by mode VCANL,H_STB -0.1 0.01 0.1 V No load 22
Driver symmetry VSYM 0.9 1 1.1 V C1 = 4.7 nF; values are ×VCC 22
CANL short circuit current ICANLsc -115 90 115 mA -3 V < VCANLshort < 18 V; t < tTxD; VTxD = 0 V 22
CANL short circuit current ICANLsc2 40 90 115 mA VCANLshort = 18 V; t < tTxD; VTxD = 0 V 22
CANH short circuit current ICANHsc -115 -90 115 mA -3 V < VCANHshort = 18 V; t < tTxD; VTxD =0 V 22
CANH short circuit current ICANHsc2 -115 -90 -40 mA VCANHshort = -3 V; t < tTxD; VTxD =0 V 23
Leakage current, CANH ICANH,lk -5 1 5 µA VCC = VIO = 0 V; 0 V < VCANH ≤ 5 V; VCANH = VCANL; 23
Leakage current, CANL ICANL,lk -5 1 5 µA VCC = VIO = 0 V; 0 V < VCANL ≤ 5 V; VCANH = VCANL 23
Output voltage difference slope, recessive to dominant Vdiff_slope_rd 42 70 V/µs 30% to 70% of measured differential bus voltage, C2 = 100 pF, RL = 60 Ω, 4.75 V < VCC < 5.25 V 23
Output voltage difference slope, dominant to recessive Vdiff_slope_dr 42 70 V/µs 70% to 30% of measured differential bus voltage, C2 = 100 pF, RL = 60 Ω, 4.75 V < VCC < 5.25 V 23
Propagation delay TxD-to-RxD tLoop 80 150 255 ns C1 = 0 pF, C2 = 100 pF, CRxD = 15 pF; (see Figure 12) 24
Propagation delay increased load TxD-to-RxD tLoop_150 80 180 330 ns C1 = 0 pF, C2 = 100 pF, CRxD = 15 pF, RL = 150 Ω 24

CAD (KiCad official)

  • Symbol: TLE9351VSJXTMA1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tle9351vsjxtma1-etched.step / tle9351vsjxtma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle9351vsjxtma1.step / tle9351vsjxtma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (32 pp, sha256 e82ede31ccae6889, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF