TLE9351SJXTMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TxD	input	Transmit data input with an internal pull-up to VCC; a low level selects the dominant state.
2	GND	power_in	Ground reference for the transceiver.
3	VCC	power_in	Transmitter supply voltage; a 1 µF decoupling capacitor to GND is recommended.
4	RxD	output	Receive data output that is driven low in the dominant state.
5	N.C.	unconnected	Not connected; the pin has no function and is not connected internally.
6	CANL	bidirectional	CAN bus low-level input/output that carries the CANL bus level.
7	CANH	bidirectional	CAN bus high-level input/output that carries the CANH bus level.
8	STB	input	Stand-by input with an internal pull-up to VCC; a low level selects normal-operating mode.

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	SOIC-8
Category	Communication Interface Chip/UART/485/232
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Transmitter supply voltage	VCC	-0.3		6	V		7
CANH and CANL DC voltage versus GND	VCANH	-40		40	V		7
Differential voltage between CANH and CANL	VCAN_Diff	-40		40	V		7
Voltage at the digital input pins STB, TxD	VMAX_IO	-0.3		6	V		7
RxD output current	IRxD	-5		5	mA		7
Junction temperature	Tj	-40		150	°C		7
Storage temperature	TS	-55		150	°C		7
ESD immunity at CANH, CANL versus GND	VESD_HBM_CAN	-10		10	kV	HBM; (100 pF via 1.5 kΩ)	7
Transmitter supply voltage (functional range)	VCC	4.75		5.25	V		8
Thermal shutdown temperature, rising	TJSD	170	180	190	°C	temperature falling: minimum 150°C	8
Thermal shutdown hysteresis	ΔT	5	10	20	K		8
Current consumption at VCC normal-operating mode, recessive state	ICC_R		1.4	4	mA	VTxD = VCC; V = 0 V; VCANH = VCANL = VCC/2	18
Current consumption at VCC normal-operating mode, dominant state	ICC_D		34	48	mA	VTxD = V = 0 V	18
Current consumption at VCC stand-by mode	ICC(STB)		5	20	µA	VTxD = VSTB = VCC	18
VCC undervoltage threshold rising edge	VCC_UV_R	3.8	4.2	4.65	V	see Figure 8	19
VCC undervoltage threshold falling edge	VCC_UV_F	3.8	4.2	4.5	V	see Figure 8	19
VCC undervoltage filter time	tVCC_UV_filter	4	6	10	µs	Figure 8	19
VCC undervoltage recovery time	tVCC_recovery		7	70	µs	see Figure 8	19
VCC power-down threshold	VCC_POD	2	2.5	3	V	see Figure 5	19
VCC delay time power-up	tPON		40	280	µs	see Figure 5	19
Receiver output RxD High level output current	IRxD_H		-2.5	-1	mA	VRxD = VCC -0.4 V; VDiff < 0.5 V	20
Receiver output RxD Low level output current	IRxD_L	1	2.5		mA	VRxD = 0.4 V; VDiff > 0.9 V	20
Transmission input TxD High level input voltage	VTxD_H			6	V	Recessive state; min printed as 0.7 x VCC	20
Transmission input TxD Low level input voltage	VTxD_L	-0.3			V	Dominant state; max printed as 0.3 x VCC	20
Internal pull-up resistor TxD	RTxD	35	55	70	kΩ		20
Input capacitance TxD	CTxD			10	pF	Not subject to production test, specified by design	20
TxD permanent dominant time-out	tTxD	1	2.3	4	ms	Normal-operating mode	20
Stand-by input STB High level input voltage	VSTB_H			6	V	stand-by mode; min printed as 0.7 x VCC	20
Stand-by input STB Low level input voltage	VSTB_L	-0.3			V	Normal-operating mode; max printed as 0.3 x VCC	20
Internal pull-up resistor STB	RSTB	35	55	70	kΩ		20
Input capacitance STB	C(STB)			10	pF	Not subject to production test, specified by design	20
Differential range dominant normal-operating mode	VDiff_D_Range	0.9		8	V	-12 V ≤ VCMR ≤ 12 V	21
Differential range recessive normal-operating mode	VDiff_R_Range	-3		0.5	V	-12V ≤ VCMR ≤ 12 V	21
Differential range dominant stand-by mode	VDiff_D_STB_Range	1.15	3	8	V	-12 V ≤ VCMR ≤ 12 V	21
Differential range recessive stand-by mode	VDiff_R_STB_Range	-3	0	0.4	V	-12 V ≤ VCMR ≤ 12 V	21
Common mode range	CMR	-12		12	V		21
Single ended internal resistance CANH	RCAN_H	6	40	50	kΩ	recessive state; -2 V ≤ VCANH ≤ 7 V; -2 V ≤ VCANL ≤ 7V	21
Single ended internal resistance CANL	RCAN_L	6	40	50	kΩ	recessive state; -2 V ≤ VCANH ≤ 7 V; -2 V ≤ VCANL ≤ 7V	21
Differential internal resistance	RDiff	12	80	100	kΩ	recessive state; -2 V ≤ VCANH ≤ 7 V; -2 V ≤ VCANL ≤ 7V	21
Input capacitance CANH, CANL versus GND	CIn			40	pF	recessive state; normal-operating mode	21
Differential input capacitance	CInDiff		4	20	pF	recessive state; normal-operating mode	21
CANL, CANH recessive output voltage normal-operating mode	VCANL,H	2	2.5	3	V	VTxD = VCC; no load	22
CANH, CANL recessive output voltage difference normal-operating mode	VDiff_R_NM	-500	-10	50	mV	VTxD = V; no load	22
CANL dominant output voltage normal-operating mode	VCANL	0.5	1.5	2.25	V	VTxD = 0 V; 50 Ω < RL < 65 Ω	22
CANH dominant output voltage normal-operating mode	VCANH	2.75	3.4	4.5	V	VTxD = 0 V; 50 Ω < RL < 65 Ω	22
Differential voltage dominant normal-operating mode	VDiff_D_NM	1.5	1.9	2.5	V	VTxD = 0 V; 50 Ω < RL < 65 Ω	22
CANH, CANL recessive output voltage difference stand-by mode	VDiff_STB	-0.2	0.001	0.2	V	No load	22
CANL, CANH recessive output voltage stand-by mode	VCANL,H_STB	-0.1	0.01	0.1	V	No load	22
CANL short circuit current	ICANLsc	-115	90	115	mA	-3 V < VCANLshort < 18 V; t < tTxD; VTxD = 0 V	22
CANH short circuit current	ICANHsc2	-115	-90	-40	mA	VCANHshort = -3 V; t < tTxD; VTxD =0 V	23
CANH, CANL output voltage difference slope, recessive to dominant	Vdiff_slope_rd		42	70	V/µs	30% to 70% of measured differential bus voltage, C2 = 100 pF, RL = 60 Ω, 4.75 V < VCC < 5.25 V	23
CANH, CANL output voltage difference slope, dominant to recessive	Vdiff_slope_dr		42	70	V/µs	70% to 30% of measured differential bus voltage, C2 = 100 pF, RL = 60 Ω, 4.75 V < VCC < 5.25 V	23
Propagation delay TxD-to-RxD	tLoop	80	150	255	ns	C1 = 0 pF, C2 = 100 pF, CRxD = 15 pF; (see Figure 12)	24
Propagation delay bus to RxD dominant to low	td(L)_R	30	90	140	ns	CRxD = 15 pF, Independent of tBit; (see Figure 12)	24
Propagation delay bus to RxD recessive to high	td(H)_R	30	100	140	ns	CRxD = 15 pF, Independent of tBit; (see Figure 12)	24
CAN activity filter time	tFilter	0.5	1.2	1.8	µs	see Figure 6	24
Bus wake-up time-out	tWake	0.8	1.5	10	ms	see Figure 6	24
Received recessive bit width at 2 MBit/s	tBit(RxD)_2M	420	450	520	ns	C2 = 100 pF; CRxD = 15 pF; tBit = 500 ns; see Figure 13	24
Transmitted recessive bit width at 5 MBit/s	tBit(Bus)_5M	155	170	210	ns	C2 = 100 pF; CRxD = 15 pF; tBit = 200 ns; see Figure 13	25
Delay time for mode change	tMode		12	20	µs		24
Bus wake-up delay time	tWU		2.5	5	µs	see Figure 6 and Figure 7	24
Junction to ambient PG-DSO-8	RthJA_DSO8		120		K/W	JEDEC JESD51-2,-7 natural convection on FR4 2s2p board	8

CAD (KiCad official)

Symbol: TLE9351SJXTMA1
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tle9351sjxtma1-etched.step / tle9351sjxtma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle9351sjxtma1.step / tle9351sjxtma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (32 pp, sha256 e94fa830fd196d8d, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TLE9351SJXTMA1

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3D Model

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