component

TLE9350XSJXTMA1

Public Made by Adom

by adom

Infineon Technologies CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232tle9350xsjxtma1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
tle9350xsjxtma1 / README.md
History Download
Ray Publish 0.1.0 b7cf0c5 5d ago

TLE9350XSJXTMA1

Infineon Technologies · CAN ICs · SOIC-8

TLE9350XSJXTMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TxD input Transmit data input with internal pull-up to VIO; low drives the dominant state, and a continuous low longer than tTxD triggers the TxD time-out that disables the transmitter.
2 GND power_in Ground.
3 VCC power_in Transmitter supply voltage (absolute max 6.0 V, functional 4.75 V to 5.25 V); a 1 µF decoupling capacitor to GND is recommended.
4 RxD output Receive data output that is low in the dominant state, with output levels referenced to VIO.
5 VIO power_in Digital supply voltage input (3.0 V to 5.5 V) that adapts the logic input and output levels to the microcontroller supply; a 100 nF decoupling capacitor to GND is recommended.
6 CANL bidirectional CAN bus low level input/output, short circuit proof to GND and supply voltage, with a DC voltage rating of -40 V to 40 V.
7 CANH bidirectional CAN bus high level input/output, short circuit proof to GND and supply voltage, with a DC voltage rating of -40 V to 40 V.
8 RM input Receive-only mode input with internal pull-up to VIO; low selects normal-operating mode and high selects receive-only mode.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Transmitter supply voltage VCC -0.3 6 V 7
Digital supply voltage VIO -0.3 6 V 7
CANH and CANL DC voltage versus GND VCANH -40 40 V 7
Differential voltage between CANH and CANL VCAN_Diff -40 40 V 7
Voltage at digital input pins RM, TxD VMAX_IO -0.3 6 V 7
RxD output current IRxD -5 5 mA 7
Junction temperature Tj -40 150 °C 7
Storage temperature TS -55 150 °C 7
Transmitter supply voltage (functional range) VCC 4.75 5.25 V 8
Digital supply voltage (functional range) VIO 3 5.5 V 8
Thermal shutdown temperature, rising TJSD 170 180 190 °C temperature falling: minimum 150°C 8
Current consumption at VCC normal-operating mode, recessive state ICC_R 1.4 4 mA VTxD = VIO; VRM = 0 V; VCANH = VCANL = VCC/2 16
Current consumption at VCC normal-operating mode, dominant state ICC_D 34 48 mA VTxD = VRM = 0 V 16
Current consumption at VIO normal-operating mode IIO 0.9 1.5 mA VRM = 0 V; VDiff = 0 V; recessive 16
Current consumption at VCC receive-only mode ICC(ROM) 0.2 1 mA VRM = VIO 16
Current consumption at VIO receive-only mode IIO(ROM) 0.8 1.5 mA VRM = VIO 16
VCC undervoltage threshold rising edge VCC_UV_R 3.8 4.2 4.65 V see Figure 6 17
VCC undervoltage threshold falling edge VCC_UV_F 3.8 4.2 4.5 V see Figure 6 17
VCC undervoltage filter time tVCC_UV_filter 4 6 10 µs Figure 6 17
VCC undervoltage recovery time tVCC_recovery 7 70 µs see Figure 6 17
VIO undervoltage threshold VIO_UV 2 2.6 3 V 17
VIO delay time power-up tPON 40 280 µs see Figure 5 17
RxD high level output current IRxD_H -2.5 -1 mA VRxD = VIO -0.4 V; VDiff < 0.5 V 18
RxD low level output current IRxD_L 1 2.5 mA VRxD = 0.4 V; VDiff > 0.9 V 18
Internal pull-up resistor TxD RTxD 35 55 70 kΩ 18
TxD permanent dominant time-out tTxD 1 2.3 4 ms Normal-operating mode 18
Internal pull-up resistor RM RRM 35 55 70 kΩ 18
Differential range dominant normal-operating mode VDiff_D_Range 0.9 8 V -12 V ≤ VCMR ≤ 12 V 19
Differential range recessive normal-operating mode VDiff_R_Range -3 0.5 V -12V ≤ VCMR ≤ 12 V 19
Common mode range CMR -12 12 V 19
Single ended internal resistance RCAN_H, RCAN_L 6 40 50 kΩ recessive state; -2 V ≤ VCANH ≤ 7 V; -2 V ≤ VCANL ≤ 7V 19
Differential internal resistance RDiff 12 80 100 kΩ recessive state; -2 V ≤ VCANH ≤ 7 V; -2 V ≤ VCANL ≤ 7V 19
Input resistance deviation between CANH and CANL ∆Ri -3 3 % recessive state; VCANH = VCANL = 5 V 19
Input capacitance CANH, CANL versus GND CIn 40 pF recessive state; normal-operating mode 19
Differential input capacitance CInDiff 4 20 pF recessive state; normal-operating mode 19
CANL, CANH recessive output voltage normal-operating mode VCANL,H 2 2.5 3 V VTxD = VIO; no load 20
CANH, CANL recessive output voltage difference normal-operating mode VDiff_R_NM -500 -10 50 mV VTxD = VIO; no load 20
CANL dominant output voltage normal-operating mode VCANL 0.5 1.5 2.25 V VTxD = 0 V; 50 Ω < RL < 65 Ω 20
CANH dominant output voltage normal-operating mode VCANH 2.75 3.4 4.5 V VTxD = 0 V; 50 Ω < RL < 65 Ω 20
Differential voltage dominant normal-operating mode VDiff_D_NM 1.5 1.9 2.5 V VTxD = 0 V; 50 Ω < RL < 65 Ω 20
Differential voltage dominant extended bus load normal-operating mode VDiff_EXT_BL 1.4 1.9 3.3 V VTxD = 0 V; 45 Ω < RL < 70 Ω 20
Differential voltage dominant high extended bus load normal-operating mode VDiff_HEXT_BL 1.5 3.5 5 V VTxD = 0 V; RL = 2240Ω; static behavior 20
CANL short circuit current ICANLsc -115 90 115 mA -3 V < VCANLshort < 18 V; t < tTxD; VTxD = 0 V 20
CANL short circuit current ICANLsc2 40 90 115 mA VCANLshort = 18 V; t < tTxD; VTxD = 0 V 20
CANH short circuit current ICANHsc -115 -90 115 mA -3 V < VCANHshort = 18 V; t < tTxD; VTxD =0 V 20
CANH short circuit current ICANHsc2 -115 -90 -40 mA VCANHshort = -3 V; t < tTxD; VTxD =0 V 20
Leakage current, CANH ICANH,lk -5 1 5 µA VCC = VIO = 0 V; 0 V < VCANH ≤ 5 V; VCANH = VCANL; 20
Leakage current, CANL ICANL,lk -5 1 5 µA VCC = VIO = 0 V; 0 V < VCANL ≤ 5 V; VCANH = VCANL 21
Output voltage difference slope, recessive to dominant Vdiff_slope_rd 42 70 V/µs 30% to 70% of measured differential bus voltage, C2 = 100 pF, RL = 60 Ω, 4.75 V < VCC < 5.25 V 21
Output voltage difference slope, dominant to recessive Vdiff_slope_dr 42 70 V/µs 70% to 30% of measured differential bus voltage, C2 = 100 pF, RL = 60 Ω, 4.75 V < VCC < 5.25 V 21
Propagation delay TxD-to-RxD tLoop 80 150 255 ns C1 = 0 pF, C2 = 100 pF, CRxD = 15 pF; (see Figure 10) 22
Propagation delay increased load TxD-to-RxD tLoop_150 80 180 330 ns C1 = 0 pF, C2 = 100 pF, CRxD = 15 pF, RL = 150 Ω 22
Propagation delay TxD to bus "low" to dominant td(L)_T 30 70 140 ns C1 = 0 pF, C2 = 100 pF, CRxD = 15 pF; (see Figure 10) 22
Propagation delay TxD to bus "high" to recessive td(H)_T 30 90 140 ns C1 = 0 pF, C2 = 100 pF, CRxD = 15 pF; (see Figure 10) 22
Propagation delay bus to RxD dominant to "low" td(L)_R 30 90 140 ns CRxD = 15 pF, Independent of tBit; (see Figure 10) 22
Propagation delay bus to RxD recessive to "high" td(H)_R 30 100 140 ns CRxD = 15 pF, Independent of tBit; (see Figure 10) 22
Delay time for mode change tMode 12 20 µs 22
Receiver timing symmetry at 2 MBit/s ∆tRec_2M -45 -23 15 ns C2 = 100 pF; CRxD = 15 pF; tBit = 500 ns; see Figure 11 23
Receiver timing symmetry at 5 MBit/s ∆tRec_5M -45 -23 15 ns C2 = 100 pF; CRxD = 15 pF; tBit = 200 ns; see Figure 11 23
Thermal resistance junction to ambient PG-DSO-8 RthJA_DSO8 120 K/W JEDEC JESD51-2,-7 at natural convection on FR4 2s2p board 8

CAD (KiCad official)

  • Symbol: TLE9350XSJXTMA1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tle9350xsjxtma1-etched.step / tle9350xsjxtma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle9350xsjxtma1.step / tle9350xsjxtma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (30 pp, sha256 98ce219251f8f533, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF