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TLE8457DSJXUMA1

Public Made by Adom

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Infineon Technologies Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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TLE8457DSJXUMA1

Infineon Technologies · Pre-ordered Chips · SOIC-8

TLE8457DSJXUMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VS power_in Battery supply voltage; decoupling capacitor required.
2 EN input Enable input with integrated pull-down resistor; logic high selects normal operation mode.
3 GND power_in Ground.
4 BUS bidirectional LIN bus input/output with integrated LIN slave termination.
5 RxD output Receive data output that monitors the LIN bus signal in normal operation mode and indicates a wake-up event in standby mode.
6 TxD input Transmit data input with integrated pull-up resistor; logic low drives a dominant signal on the LIN bus.
7 NRST output Undervoltage reset output with integrated pull-up resistor; logic low during reset.
8 VCC power_out Voltage regulator output (3.3 V on the TLE8457D); output capacitor requirements are given in the functional device characteristics.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply input voltage VS -0.3 45 V LIN Spec 2.2A (Par. 11) 17
Bus input voltage VBUS -27 40 V 17
Logic voltages at EN and TxD Vlogic,in -0.3 7 V 17
Voltage regulator output VCC -0.3 7 V 17
Output current at RxD IRxD -15 15 mA 17
Output current at NRST INRST 10 mA 17
Junction temperature Tj -40 150 °C 17
Storage temperature Ts -55 150 °C 17
ESD at VS and BUS vs. GND VESD -8 8 kV Human body model (100 pF via 1.5 kΩ) 17
ESD all other pins VESD -2 2 kV Human body model (100 pF via 1.5 kΩ) 17
ESD corner pins VESD -750 750 V Charged device model 17
ESD at all other pins VESD -500 500 V Charged device model 17
Supply voltage range for normal operation VS(nor) 5.5 28 V LIN Spec 2.2A Param. 10 18
Extended supply voltage range for operation VS(ext) 3 40 V Parameter deviations possible 18
Output capacitor range CVCC 1 µF 18
Output capacitor ESR ESR(CVCC) 5 Ω f = 10 kHz 18
Junction temperature Tj -40 150 °C 18
Thermal resistance junction to ambient, PG-DSO-8 RthJA 130 K/W JESD51-2,-5,-7, natural convection, FR4 2s2p 19
Thermal shutdown temperature TJSD 160 180 200 °C TJSD increasing 19
Thermal shutdown hysteresis ΔT 10 K TJSD decreasing 19
Current consumption at VS, recessive IS,rec 0.1 0.3 0.7 mA ICC = 50 µA; without RLIN; TxD = high; VBUS = VS; NRST=high 20
Current consumption at VS, dominant IS,dom 0.1 1 3 mA ICC = 50 µA; without RLIN; TxD = low; VBUS = 0 V; NRST=high 20
Current consumption at VS, dominant max IS,dom_max 70 71 73 mA ICC = 70 mA; without RLIN; TxD = low; VBUS = 0 V; NRST=high 20
Current consumption in standby mode IS,standby 20 40 µA Standby mode; ICC = 50 µA; VS = VBUS = 13.5 V; NRST = TxD = high 20
Current consumption in sleep mode IS,Sleep 7 16 µA Sleep mode; VS = 13.5 V; VBUS =VS; VCC =0V 20
Sleep mode current, BUS shorted to GND IS,SC_GND 250 800 µA Sleep Mode; VS = 13.5 V; VBUS = 0 V; VCC =0V 20
Power-on reset level, VS on VS,PON 3 V 20
Undervoltage threshold, VS on VS,UV,ON 4.7 5.15 5.5 V Rising edge 20
Undervoltage threshold, VS off VS,UV,OFF 4.4 4.85 5.2 V Falling edge 20
Undervoltage hysteresis on VS VS,UV,hys 200 300 mV 20
EN high level input voltage VEN,ON 2 V 20
EN low level input voltage VEN,OFF 0.8 V 20
EN input hysteresis VEN,hys 50 200 mV 20
EN pull-down resistance REN 15 30 60 kΩ 20
Delay time for mode change, EN low tMODE,LOW 10 50 µs 20
Delay time for mode change, EN high tMODE,HIGH 5 µs 21
NRST high level leakage current INRST,H 5 µA 21
NRST low level output voltage VNRST 0.4 V INRST = 1.5 mA; VCC > 1 V 21
Reset time tRST 4 10 16 ms 21
NRST internal pull-up resistance RNRST 5 10 20 kΩ 21
Output voltage (3.3 V version) VCC 3.234 3.3 3.366 V 0.05 mA < ICC < 70 mA; 4.066 V < VS < 28 V 21
Output voltage drop VDR 380 770 mV ICC < 70 mA 21
Output voltage drop, 50 mA VDR,50 280 550 mV ICC < 50 mA 21
Output voltage drop, 20 mA VDR,20 110 220 mV ICC < 20 mA 21
Output current limitation ICC,lim -150 -70 mA 0 V < VCC < 3.1 V 22
Load regulation ∆VCC,lo 25 50 mV 0.05 mA < ICC < 70 mA; VS = 13.5 V 22
Line regulation ∆VCC,li 25 50 mV ICC = 1 mA; 4.066 V < VS < 28 V 22
Power supply ripple rejection PSRR 50 60 dB ICC = 50 mA; f = 100 Hz; Vr = 0.5 Vpp; VS = 13.5 V 22
Undervoltage reset threshold VCC,UV 2.82 2.9 2.96 V VCC decreasing 22
Undervoltage reset hysteresis VCC,UV,hy 33 66 mV 22
Undervoltage detection time tdet,RST 1 20 µs VCC = 2.31 V; CNRST = 20 pF 22
RxD high level output voltage VRxD,H 0.8 V IRxD = -2 mA; VBUS = VS (min is 0.8 ×VCC) 22
RxD low level output voltage VRxD,L 0.2 V IRxD = 2 mA; VBUS =0V (max is 0.2 ×VCC) 22
TxD high level input voltage VTxD,H 0.7 V Recessive state (min is 0.7 ×VCC) 22
TxD low level input voltage VTxD,L 0.3 V Dominant state (max is 0.3 ×VCC) 22
TxD input hysteresis VTxD,hys 200 mV 22
TxD pull-up resistance RTxD 15 30 60 kΩ 22
TxD time-out tTxD 8 18 28 ms 22
TxD recessive release time tto,rec 10 µs 22
Receiver threshold, recessive to dominant Vth_dom 0.4 0.44 V VS < 18 V (values are ×VS) 22
Receiver threshold, dominant to recessive Vth_rec 0.56 0.6 V VS < 18 V (values are ×VS) 22
Receiver center voltage VBUS_CNT 0.475 0.5 0.525 V LIN Spec 2.2A (Par. 19); VS < 18V (values are ×VS) 22
Receiver hysteresis VHYS 0.07 0.12 0.175 V LIN Spec 2.2A (Par. 20); VS < 18 V (values are ×VS) 23
BUS short-circuit current IBUS_LIM 40 85 125 mA VBUS = 18 V; LIN Spec 2.2A (Par. 12) 23
BUS pull-up resistance Rslave 20 40 60 kΩ LIN Spec 2.2A (Par. 26) 23
Dominant time for bus wake-up tWK,bus 30 150 µs 23

CAD (KiCad official)

  • Symbol: TLE8457DSJXUMA1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tle8457dsjxuma1-etched.step / tle8457dsjxuma1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle8457dsjxuma1.step / tle8457dsjxuma1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (31 pp, sha256 78e2b8c62087bacd, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF