# TLE7250GVIOXUMA2

**Infineon Technologies** · CAN ICs · SOIC-8

TLE7250GVIOXUMA2 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TxD | input | Transmit data input with internal pull-up to VIO; logic low drives the dominant state on the bus. |
| 2 | GND | power_in | Ground. |
| 3 | VCC | power_in | Transceiver supply voltage (4.5 V to 5.5 V functional range) requiring a 100 nF decoupling capacitor to GND. |
| 4 | RxD | output | Receive data output that is low in the dominant state, with levels set by VIO. |
| 5 | VIO | power_in | Digital supply input (3.0 V to 5.5 V) that adapts logic input and output levels to the microcontroller supply, requiring a 100 nF decoupling capacitor to GND. |
| 6 | CANL | bidirectional | CAN bus low level input/output that is low in the dominant state and short-circuit proof, with ±40 V DC maximum rating. |
| 7 | CANH | bidirectional | CAN bus high level input/output that is high in the dominant state and short-circuit proof, with ±40 V DC maximum rating. |
| 8 | NEN | input | Not Enable input with internal pull-up to VIO; low selects normal-operating mode and high selects stand-by mode. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.3 |  | 6 | V |  | 13 |
| Logic supply voltage | VIO | -0.3 |  | 6 | V |  | 13 |
| CANH DC voltage against GND | VCANH | -40 |  | 40 | V |  | 13 |
| CANL DC voltage against GND | VCANL | -40 |  | 40 | V |  | 13 |
| Differential voltage between CANH and CANL | VCAN diff | -40 |  | 40 | V |  | 13 |
| Logic voltage at logic input pins NEN, TxD | VMax_In | -0.3 |  | 6 | V |  | 13 |
| Logic voltage at logic output pin RxD | VMax_Out | -0.3 |  |  | V | max printed as VIO | 13 |
| Junction temperature | Tj | -40 |  | 150 | °C |  | 13 |
| Storage temperature | TS | -55 |  | 150 | °C |  | 13 |
| ESD immunity at CANH, CANL against GND | VESD_HBM_CAN | -8 |  | 8 | kV | HBM (100pF via 1.5 kΩ) | 13 |
| ESD immunity at all other pins | VESD_HBM_All | -2 |  | 2 | kV | HBM (100pF via 1.5 kΩ) | 13 |
| ESD immunity to GND (all pins) | VESD_CDM | -750 |  | 750 | V | CDM | 13 |
| Transceiver supply voltage | VCC | 4.5 |  | 5.5 | V |  | 14 |
| Logical supply voltage | VIO | 3 |  | 5.5 | V |  | 14 |
| Junction temperature | Tj | -40 |  | 150 | °C |  | 14 |
| Thermal resistance junction to ambient | RthJA |  | 130 |  | K/W | JESD51-2,-7 natural convection, FR4 2s2p board | 14 |
| Thermal shut-down temperature | TJSD | 150 | 175 | 200 | °C |  | 14 |
| Thermal shut-down hysteresis | ΔT |  | 10 |  | K |  | 14 |
| Current consumption at VCC (recessive) | ICC |  | 2 | 6 | mA | "recessive" state; VTxD = VIO | 15 |
| Current consumption at VCC (dominant) | ICC |  | 35 | 60 | mA | "dominant" state; VTxD = "low" | 15 |
| Current consumption at VIO | IIO |  | 0.2 | 1 | mA | normal-operating mode; NEN = "low" | 15 |
| Current consumption stand-by mode | ICC(STB) |  | 4 | 15 | μA | VCC =VIO = 5 V, TxD = VIO, NEN = VIO | 15 |
| Current consumption stand-by mode | IIO(STB) |  | 2 | 10 | μA | VCC =VIO = 5 V, TxD = VIO, NEN = VIO | 15 |
| VCC undervoltage monitor | VCC(UV) | 1.3 | 3.2 | 4.3 | V |  | 15 |
| VIO undervoltage monitor | VIO(UV) | 1 | 2.4 | 3 | V |  | 15 |
| VCC and VIO undervoltage delay time | tDelay(UV) |  |  | 50 | μs | see Figure 6 | 15 |
| "High" level output current RxD | IRD,H |  | -4 | -2 | mA | VRxD = VIO - 0.4 V, VDIFF < 0.5 V | 15 |
| "Low" level output current RxD | IRD,L | 2 | 4 |  | mA | VRxD = 0.4 V, VDIFF > 0.9 V | 15 |
| TxD "High" level input voltage threshold | VTD,H |  | 0.5 | 0.7 | xVIO | "recessive" state | 15 |
| TxD "Low" level input voltage threshold | VTD,L | 0.3 | 0.4 |  | xVIO | "dominant" state | 15 |
| TxD pull-up resistance | RTD | 10 | 25 | 50 | kΩ |  | 15 |
| TxD permanent dominant disable time | tTxD | 0.3 |  | 1 | ms |  | 15 |
| NEN "High" level input voltage threshold | VNEN,H |  | 0.5 | 0.7 | xVIO | stand-by mode | 16 |
| NEN "Low" level input voltage threshold | VNEN,L | 0.3 | 0.4 |  | xVIO | normal-operating mode | 16 |
| NEN pull-up resistance | RNEN | 10 | 25 | 50 | kΩ |  | 16 |
| Differential receiver threshold dominant | VDIFF,(D) |  | 0.75 | 0.9 | V | normal-operating mode | 16 |
| Differential receiver threshold recessive | VDIFF,(R) | 0.5 | 0.65 |  | V | normal-operating mode | 16 |
| Differential receiver input range dominant | Vdiff,rdN | 0.9 |  | 5 | V | normal-operating mode | 16 |
| Differential receiver input range recessive | Vdiff,drN | -1 |  | 0.5 | V | normal-operating mode | 16 |
| Common mode range | CMR | -12 |  | 12 | V | VCC = 5 V | 16 |
| CANH, CANL input resistance | Ri | 10 | 20 | 30 | kΩ | "recessive" state | 16 |
| Differential input resistance | Rdiff | 20 | 40 | 60 | kΩ | "recessive" state | 16 |
| Input resistance deviation between CANH and CANL | ΔRi | -3 |  | 3 | % | "recessive" state | 16 |
| Input capacitance CANH, CANL versus GND | CIN |  | 20 | 40 | pF | VTxD = VIO | 16 |
| Differential input capacitance | CInDiff |  | 10 | 20 | pF | VTxD = VIO | 16 |
| CANL/CANH recessive output voltage | VCANL/H | 2 | 2.5 | 3 | V | no load; VTxD = VIO | 16 |
| CANH, CANL recessive output voltage difference | Vdiff | -500 |  | 50 | mV | no load; VTxD = VIO | 16 |
| CANL dominant output voltage | VCANL | 0.5 |  | 2.25 | V | 4.75 V ≤ VCC ≤ 5.25 V, VTxD = 0 V, 50 Ω < RL < 65 Ω | 16 |
| CANH dominant output voltage | VCANH | 2.75 |  | 4.5 | V | 4.75 V ≤ VCC ≤ 5.25 V, VTxD = 0 V, 50 Ω < RL < 65 Ω | 16 |
| CANH, CANL dominant output voltage difference | Vdiff | 1.5 |  | 3 | V | 4.75 V ≤ VCC ≤ 5.25 V, VTxD = 0 V, 50 Ω < RL < 65 Ω | 16 |
| Driver symmetry | VSYM | 4.5 |  | 5.5 | V | VTxD = 0 V, VCC = 5 V, 50 Ω < RL < 65 Ω | 16 |
| CANL short-circuit current | ICANLsc | 40 | 80 | 100 | mA | VTxD = 0 V, VCC = 5 V, t < tTxD, VCANLshort = 18 V | 17 |
| CANH short-circuit current | ICANHsc | -100 | -80 | -40 | mA | VTxD = 0 V, VCC = 5 V, t < tTxD, VCANHshort = 0 V | 17 |
| Leakage current CANH | ICANH,lk | -5 | 0 | 5 | μA | VCC = 0 V, VCANH = VCANL, 0V< VCANH <5V | 17 |
| Leakage current CANL | ICANL,lk | -5 | 0 | 5 | μA | VCC = 0 V, VCANH = VCANL, 0V< VCANL <5V | 17 |
| Propagation delay TxD-to-RxD low | td(L),TR | 30 | 180 | 255 | ns | CL = 100 pF, VCC = 5 V, CRxD = 15 pF | 17 |
| Propagation delay TxD-to-RxD high | td(H),TR | 30 | 200 | 255 | ns | CL = 100 pF, VCC = 5 V, CRxD = 15 pF | 17 |
| Time for mode change | tMode |  |  | 10 | μs |  | 17 |

## CAD (KiCad official)

- Symbol: `TLE7250GVIOXUMA2`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tle7250gvioxuma2-etched.step` / `tle7250gvioxuma2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tle7250gvioxuma2.step` / `tle7250gvioxuma2.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](https://www.infineon.com/dgdl/Infineon-TLE7250GVIO-DS-v01_10-EN.pdf?fileId=5546d46259d9a4bf015a3cf633b45e56) (23 pp, sha256 `a36ee8c58b63f36d`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tle7250gvioxuma2-datasheet.pdf)