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TLE6251DS

Public Made by Adom

by adom

Infineon Technologies CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TLE6251DS

Infineon Technologies · CAN ICs · SOIC-8

TLE6251DS from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TxD input CAN transmit data input with a 20 kΩ pull-up that is LOW in the dominant state.
2 GND power_in Ground reference for the transceiver.
3 VCC power_in 5 V supply input that must be blocked to GND with a 100 nF ceramic capacitor.
4 RxD output CAN receive data output that is LOW in the dominant state and also signals wake-up in stand-by mode.
5 SPLIT output Split termination output that stabilizes the recessive common mode voltage at 0.5 VCC in normal mode.
6 CANL bidirectional Low CAN bus line that is LOW in the dominant state.
7 CANH bidirectional High CAN bus line that is HIGH in the dominant state.
8 STB input Mode control input with an internal pull-up of 10 to 40 kΩ, where HIGH selects stand-by mode.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.3 5.5 V 12
CAN bus voltage (CANH, CANL) VCANH/L -32 40 V 12
CAN bus differential voltage CANH, CANL, SPLIT VCAN diff -40 40 V CANH - CANL < /40 V/; CANH - SPLIT < /40 V/; CANL - SPLIT < /40 V/ 12
Input voltage at SPLIT VSPLIT -27 40 V 12
Logic voltages at STB, TxD, RxD VI -0.3 V 0 V < VCC < 5.5 V; max printed as VCC 12
Electrostatic discharge voltage at CANH, CANL, SPLIT vs. GND VESD -6 6 kV human body model (100 pF via 1.5 kΩ) 12
Electrostatic discharge voltage VESD -2 2 kV human body model (100 pF via 1.5 kΩ) 12
Storage temperature Tj -40 150 °C 12
Supply voltage VCC 4.75 5.25 V 13
Junction temperature Tj -40 150 °C 13
Junction ambient thermal resistance Rthj-a 185 K/W 13
Thermal shutdown temperature TjsD 150 190 °C 13
Thermal shutdown hysteresis ΔT 10 K 13
Current consumption recessive state ICC 6 10 mA recessive state; VTxD = VCC 14
Current consumption dominant state ICC 45 70 mA dominant state; VTxD = 0 V 14
Current consumption stand-by mode ICC,stb 20 30 µA stand-by mode; TxD = high 14
HIGH level output current RxD IRD,H -4 -2 mA VRD = 0.8 × VCC 14
HIGH level output current RxD stand-by mode IRD,H -100 µA stand-by mode 14
LOW level output current RxD IRD,L 2 4 mA VRD = 0.2 × VCC 14
Short circuit current RxD ISC,RxD 15 20 mA 14
HIGH level input voltage threshold TxD VTD,H 2 V recessive state 14
LOW level input voltage threshold TxD VTD,L 0.8 V dominant state 14
TxD pull-up resistance RTD 10 20 40 kΩ 14
HIGH level input voltage threshold STB VSTB,H 2 V normal mode 14
LOW level input voltage threshold STB VSTB,L 0.8 V receive-only mode 14
STB pull-up resistance RSTB 10 20 40 kΩ 14
Split output voltage VSPLIT 0.3 0.5 0.7 ×VCC normal mode; -500 µA < ISPLIT < 500 µA 15
Split output voltage no load VSPLIT 0.45 0.5 0.55 ×VCC normal mode; no Load 15
Split leakage current ISPLIT -5 0 5 µA standby mode; -22 V < VSPLIT < 35 V 15
Differential receiver threshold voltage normal mode recessive to dominant Vdiff,rdN 0.8 0.9 V recessive to dominant 15
Differential receiver threshold voltage normal mode dominant to recessive Vdiff,drN 0.5 0.6 V dominant to recessive 15
Differential receiver threshold low power mode recessive to dominant Vdiff,rdLP 0.9 1.15 V recessive to dominant 15
Differential receiver threshold low power mode dominant to recessive Vdiff,drLP 0.4 0.8 V dominant to recessive 15
Common mode range CMR -12 12 V VCC = 5 V 15
CANH, CANL input resistance Ri 10 20 30 kΩ recessive state 15
Differential input resistance Rdiff 20 40 60 kΩ recessive state 15
CANL/CANH recessive output voltage VCANL/H 2 2.5 3 V VTxD = VCC; no load 15
CANH, CANL recessive output voltage difference Vdiff -500 50 mV VTxD = VCC; no load 15
CANL dominant output voltage VCANL 0.5 2.25 V VTxD = 0 V; VCC = 5 V 15
CANH dominant output voltage VCANH 2.75 4.5 V VTxD = 0 V; VCC = 5 V 15
CANH, CANL dominant output voltage difference Vdiff 1.5 3 V VTxD = 0 V; VCC = 5 V 16
CANL short circuit current ICANLsc 50 80 200 mA VCANLshort = 18 V 16
CANH short circuit current ICANHsc -200 -80 -50 mA VCANHshort = 0 V 16
Leakage current CANH, CANL ICANH,L,lk -5 µA VCC = 0 V; 0 V < VCANH,L < 5 V 16
Propagation delay TxD-to-RxD LOW recessive to dominant td(L),TR 150 255 ns CL = 47 pF; RL = 60 Ω; VCC = 5 V; CRxD = 15 pF 16
Propagation delay TxD-to-RxD HIGH dominant to recessive td(H),TR 150 255 ns CL = 47 pF; RL = 60 Ω; VCC = 5 V; CRxD = 15 pF 16
Propagation delay TxD LOW to bus dominant td(L),T 50 120 ns CL = 47 pF; RL = 60 Ω; VCC = 5 V 16
Propagation delay TxD HIGH to bus recessive td(H),T 50 120 ns CL = 47 pF; RL = 60 Ω; VCC = 5 V 16
Propagation delay bus dominant to RxD LOW td(L),R 100 135 ns CL = 47 pF; RL = 60 Ω; VCC = 5 V; CRxD = 15 pF 16
Propagation delay bus recessive to RxD HIGH td(H),R 100 135 ns CL = 47 pF; RL = 60 Ω; VCC = 5 V; CRxD = 15 pF 16
Min. dominant time for bus wake-up signal RxD high to low tWU1 0.75 3 5 µs tWU1 = td(L),R + tWU; see Figure 6 16
Min. recessive time for bus wake-up signal RxD low to high tWU2 0.75 3 5 µs tWU2 = td(H),R + tWU; see Figure 6 17
TxD permanent dominant disable time tTxD 0.3 1 ms 17
Split termination output resistance RSPLIT 600 Ω 15
TxD input hysteresis VTD hys 200 mV 14
STB input hysteresis VSTB hys 200 mV 14
Differential receiver hysteresis Vdiff,hys 200 mV 15

CAD (KiCad official)

  • Symbol: TLE6251DS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tle6251ds-etched.step / tle6251ds-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle6251ds.step / tle6251ds.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (22 pp, sha256 2b649fbd541a0a75, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF