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TLE4284DV

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Infineon Technologies Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TO-252. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLE4284DV

Infineon Technologies · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TO-252

TLE4284DV from Infineon Technologies, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADJ input Adjust pin; the output voltage is set by an external voltage divider between Q, ADJ and GND, with the internal reference typically 1.25 V (VREF = VQ - VADJ).
2 Q power_out Output pin, also connected to the heatsink tab; connect to GND via an output capacitor CQ ≥ 10 µF with ESR ≤ 10 Ω.
3 I power_in Input pin; the input voltage must be in the range VQnom + VDR < VI < 40 V, with absolute maximum rating of -0.3 V to 40 V.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TO-252
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reference voltage VREF 1.2 1.25 1.3 V 6
Line regulation ∆VQ 0.5 1.5 % 3 V ≤ (VI, VQ) ≤ 40 V 6
Load regulation ∆VQ 0.2 0.4 % 10 mA ≤ IQ ≤ 800 mA; VI = 3.0 V; VQ = VREF 6
Load regulation ∆VQ 0.25 0.5 % 10 mA ≤ IQ ≤ 1.0 A; VI = 3.0 V; VQ = VREF 6
Dropout voltage VDR 1 1.2 V IQ = 100 mA 6
Dropout voltage VDR 1.05 1.3 V IQ = 500 mA 6
Dropout voltage VDR 1.1 1.35 V IQ = 800 mA 6
Dropout voltage VDR 1.3 1.4 V IQ = 1.0 A 6
Current consumption Iq 100 120 µA IQ = 10 mA 6
Adjust current IADJ 75 120 µA IQ = 10 mA 6
Adjust current change ∆IADJ 2 5 µA IQ = 10 mA; 3 V ≤ (VI, VQ) ≤ 40 V 6
Temperature stability 0.6 % 6
Minimum load current IQ 1 5 mA VI < 40 V; VQ = VREF 6
Current limit IQmax 1000 2200 mA 1.4V < VI - VQ < 18V; VQ = Vnom -100 mV 6
Current limit IQmax 50 200 mA VI = 40 V; VQ = Vnom -100 mV; Tj = 25 °C 6
RMS output noise 30 ppm ppm of VQ; Tj = 25 °C; 10 Hz ≤ f ≤ 10 kHz 6
Power supply ripple rejection PSRR 65 dB VQ = 10 V, fr = 120 Hz, Vr = 0.5 VPP, CADJ = 0 µF 7
Input - output voltage difference VI - VQ -0.3 40 V 4
Input voltage VI -0.3 40 V 4
Adjust voltage (variable version only) VADJ -0.3 40 V 4
Storage temperature Tstg -50 150 °C 4
Junction temperature Tj -40 150 °C 4
ESD susceptibility Human Body Model (HBM) 4 kV 4
ESD susceptibility Charged Device Model (CDM) 1 kV 4
Input voltage (operating range) VI 40 V 5
Junction temperature (operating range) Tj -40 150 °C 5
Output capacitor CQ 10 µF 21
Output capacitor ESR ESR 0.1 10 Ω 21
Output capacitor when CADJ is placed CQ 22 µF CADJ placed at the adjust pin 21
Junction-ambient thermal resistance (footprint only) Rthja 144 K/W PG-TO252-3-11 footprint only 5
Junction-ambient thermal resistance (300 mm² heat sink area) Rthja 78 K/W PG-TO252-3-11, 300 mm² heat sink area 5
Junction-ambient thermal resistance (600 mm² heat sink area) Rthja 54 K/W PG-TO252-3-11, 600 mm² heat sink area 5
Junction-case thermal resistance Rthjc 4 K/W 5

CAD (KiCad official)

  • Symbol: TLE4284DV
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: tle4284dv-etched.step / tle4284dv-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle4284dv.step / tle4284dv.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (25 pp, sha256 c9ece05c4b7c663a, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF