# TLE42754G

**Infineon Technologies** · Linear Voltage Regulators (LDO) · TO-263-5

TLE42754G from Infineon Technologies, in a TO-263-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | input | Input for compensating line influences; a capacitor to GND close to the IC terminals is recommended. |
| 2 | RO | output | Open-collector reset output that requires an external pull-up resistor to a positive potential; leave open if the reset function is not needed. |
| 3 | GND | power_in | Ground, internally connected to the tab (this pin is specified for the TLE42754G PG-TO263-5 variant only). |
| 4 | D | passive | Reset delay timing; connect a ceramic capacitor to GND to set the reset delay time, or leave open if the reset function is not needed. |
| 5 | Q | power_out | Regulated 5 V output; block to GND with a capacitor close to the IC terminals, respecting the CQ and ESR values in the Functional Range table (CQ minimum 22 µF, ESR maximum 3 Ω at 10 kHz). |
| 6 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | TO-263-5 |
| Category | Power Management ICs |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VI | -42 |  | 45 | V |  | 7 |
| Output Voltage | VQ | -0.3 |  | 7 | V |  | 7 |
| Reset Output Voltage | VRO | -0.3 |  | 25 | V |  | 7 |
| Reset Delay Voltage | VD | -0.3 |  | 7 | V |  | 7 |
| Junction Temperature | Tj | -40 |  | 150 | °C |  | 7 |
| Storage Temperature | Tstg | -50 |  | 150 | °C |  | 7 |
| ESD Absorption HBM | VESD,HBM | -2 |  | 2 | kV | Human Body Model (HBM) | 7 |
| ESD Absorption CDM | VESD,CDM | -500 |  | 500 | V | Charge Device Model (CDM) | 7 |
| ESD Absorption CDM at corner pins | VESD,CDM | -750 |  | 750 | V | Charge Device Model (CDM) at corner pins | 7 |
| Input Voltage | VI | 5.5 |  | 42 | V |  | 8 |
| Output Capacitor Requirement for Stability | CQ | 22 |  |  | µF | worst-case capacitance tolerance of 30% | 8 |
| Output Capacitor Requirement for Stability ESR | ESR(CQ) |  |  | 3 | Ω | f = 10 kHz | 8 |
| Junction Temperature (functional range) | Tj | -40 |  | 150 | °C |  | 8 |
| Output Voltage | VQ | 4.9 | 5 | 5.1 | V | 1 mA < IQ < 450 mA; 9 V < VI < 28 V | 11 |
| Output Current Limitation | IQ,max | 450 |  | 1100 | mA | VQ = 4.8V | 11 |
| Load Regulation steady-state | ΔVQ,load | -30 | -15 |  | mV | IQ = 5 mA to 400 mA; VI = 8 V | 11 |
| Line Regulation steady-state | ΔVQ,line |  | 5 | 15 | mV | VI = 8 V to 32 V; IQ = 5 mA | 11 |
| Dropout Voltage | Vdr |  | 250 | 500 | mV | IQ = 300 mA | 11 |
| Overtemperature Shutdown Threshold | Tj,sd | 151 |  | 200 | °C | Tj increasing | 11 |
| Current Consumption | Iq |  | 150 | 200 | µA | IQ = 1 mA; Tj = 25 °C | 14 |
| Current Consumption | Iq |  | 150 | 220 | µA | IQ = 1 mA; Tj = 85 °C | 14 |
| Current Consumption | Iq |  | 5 | 10 | mA | IQ = 250 mA | 14 |
| Current Consumption | Iq |  | 15 | 25 | mA | IQ = 400 mA | 14 |
| Output Undervoltage Reset Switching Threshold | VRT | 4.5 | 4.65 | 4.8 | V | VQ decreasing | 19 |
| Reset Output Low Voltage | VRO,low |  | 0.2 | 0.4 | V | 1 V ≤ VQ ≤ VRT; IRO = 0.2 mA | 19 |
| Reset Output Sink Current Capability | IRO,max | 0.2 |  |  | mA | 1 V ≤ VQ ≤ VRT; VRO = 5 V | 19 |
| Reset Output Leakage Current | IRO,leak |  | 0 | 10 | µA | VRO = 5 V | 19 |
| Reset Output External Pull-up Resistor to VQ | RRO | 5 |  |  | kΩ | 1 V ≤ VQ ≤ VRT; VRO ≤ 0.4 V | 19 |
| Power On Reset Delay Time | trd | 10 | 16 | 22 | ms | CD = 47 nF | 19 |
| Delay Capacitor Reset Discharge Time | trr,d |  | 0.5 | 1 | µs | CD = 47 nF | 19 |
| Internal Reset Reaction Time | trr,int |  | 4 | 7 | µs | CD = 0 nF | 19 |
| Reset Reaction Time | trr,total |  | 4.5 | 8 | µs | CD = 47 nF | 19 |
| Junction to Case (TLE42754G PG-TO263-5) | RthJC |  | 3.7 |  | K/W |  | 9 |
| Junction to Ambient (TLE42754G PG-TO263-5) | RthJA |  | 22 |  | K/W | FR4 2s2p board | 9 |
| Junction to Ambient (TLE42754G PG-TO263-5) | RthJA |  | 70 |  | K/W | FR4 1s0p board, footprint only | 9 |
| Junction to Ambient (TLE42754G PG-TO263-5) | RthJA |  | 42 |  | K/W | FR4 1s0p board, 300 mm2 heatsink area on PCB | 9 |
| Junction to Ambient (TLE42754G PG-TO263-5) | RthJA |  | 33 |  | K/W | FR4 1s0p board, 600 mm2 heatsink area on PCB | 9 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs |  | ESD Absorption VESD,HBM -2, 2 kV Human Body Model | 7 |

## CAD (KiCad official)

- Symbol: `TLE42754G`
- Footprint: `Package_TO_SOT_SMD:TO-263-5_TabPin6`
- 3D model: TO-263-5 (KiCad packages3D, STEP)
- 3D model files: `tle42754g-etched.step` / `tle42754g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tle42754g.step` / `tle42754g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/tle42754g-datasheet.pdf) (29 pp, sha256 `903108b634588660`, retrieved 2026-11-05, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tle42754g-datasheet.pdf)