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TLE4274D V50
Public Made by Adomby adom
Infineon Technologies Linear Voltage Regulators (LDO), TO-252. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLE4274D V50
Infineon Technologies · Linear Voltage Regulators (LDO) · TO-252
TLE4274D V50 from Infineon Technologies, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | power_in | Input supply (operating range 5.5 V to 40 V for the V50 version); block to ground directly at the IC with a ceramic capacitor. |
| 2 | GND | power_in | Ground. |
| 3 | Q | power_out | Regulated 5 V output (400 mA max); block to ground with a capacitor ≥ 22 µF, ESR ≤ 3 Ω. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | TO-252 |
| Category | Power Management ICs |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage V50 (high current) | VQ | 4.8 | 5 | 5.2 | V | 5 mA < IQ < 400 mA, 6 V < VI < 28 V | 7 |
| Output voltage V50 (high input) | VQ | 4.8 | 5 | 5.2 | V | 5 mA < IQ < 200 mA, 6 V < VI < 40 V | 7 |
| Output current limitation | IQ | 400 | 600 | mA | 1) | 7 | |
| Current consumption | Iq | 100 | 220 | mA | IQ = 1 mA | 7 | |
| Current consumption | Iq | 8 | 15 | mA | IQ = 250 mA | 7 | |
| Current consumption | Iq | 20 | 30 | mA | IQ = 400 mA | 7 | |
| Drop voltage | Vdr | 250 | 500 | mV | IQ = 250 mA, Vdr = VI - VQ | 7 | |
| Load regulation | ΔVQ | 20 | 50 | mV | IQ = 5 mA to 400 mA | 7 | |
| Line regulation | ΔVQ | 10 | 25 | mV | ΔVI = 12 V to 32 V, IQ = 5 mA | 7 | |
| Power supply ripple rejection | PSRR | 60 | dB | fr = 100 Hz, Vr = 0.5 Vpp | 7 | ||
| Temperature output voltage drift | ΔVQ/ΔT | 0.5 | mV/K | 7 | |||
| Input voltage (absolute maximum) | VI | -42 | 45 | V | Tj = -40°C to 150°C | 5 | |
| Output voltage (absolute maximum) | VQ | -1 | 40 | V | Tj = -40°C to 150°C | 5 | |
| Ground current (absolute maximum) | IGND | 100 | mA | Tj = -40°C to 150°C | 5 | ||
| Junction temperature (absolute maximum) | Tj | 150 | °C | 5 | |||
| Storage temperature | Tstg | -50 | 150 | °C | 5 | ||
| Input voltage, V50 | VI | 5.5 | 40 | V | 5 | ||
| Junction temperature | Tj | -40 | 150 | °C | 5 | ||
| Thermal resistance junction-ambient | Rthja | 78 | K/W | PG-TO252-3, worst case, zero airflow, 80×80×1.5 mm3 PCB, 300 mm2 heatsink area | 5 | ||
| Thermal resistance junction-case | Rthjc | 4 | K/W | 5 |
CAD (KiCad official)
- Symbol:
TLE4274D V50 - Footprint:
Package_TO_SOT_SMD:TO-252-2 - 3D model: TO-252 (KiCad packages3D, STEP)
- 3D model files:
tle4274d-v50-etched.step/tle4274d-v50-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tle4274d-v50.step/tle4274d-v50.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (13 pp, sha256
fa4fba519de19d2c, retrieved 2026-10-22, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).