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TLE42644G
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Infineon Technologies Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-223-4. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TLE42644G
Infineon Technologies · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223-4
TLE42644G from Infineon Technologies, in a SOT-223-4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | power_in | Input pin, rated for input voltage VI of 5.5 V to 40 V in the functional range (absolute maximum -30 V to 45 V), and should be blocked to ground directly at the IC with a ceramic capacitor (100 nF to 470 nF recommended). |
| 2 | GND | power_in | Ground reference for all voltages of the regulator, to be connected to the system ground. |
| 3 | Q | power_out | Regulated 5 V output (VQ,nom = 5 V, ±2 % up to 50 mA and ±3 % up to 100 mA), which must be blocked to ground with a capacitor of at least 10 µF with ESR below 2 Ω at 10 kHz placed close to the IC terminals. |
| 4 | GND | power_in | Ground connected internally to the leadframe and GND, which must be connected to GND and the heatsink area for thermal dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-223-4 |
| Category | Power Management (PMIC) |
| Pins | 4 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VI | -30 | 45 | V | 5 | ||
| Output voltage | VQ | -0.3 | 32 | V | 5 | ||
| Junction temperature | Tj | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -50 | 150 | °C | 5 | ||
| ESD Absorption | VESD,HBM | -3 | 3 | kV | Human Body Model (HBM) | 5 | |
| ESD Absorption | VESD,CDM | -1500 | 1500 | V | Charge Device Model (CDM) at all pins | 5 | |
| Input voltage | VI | 5.5 | 40 | V | 5 | ||
| Output Capacitor's Requirements for Stability | CQ | 10 | µF | 5 | |||
| Output Capacitor's Requirements for Stability ESR | ESR(CQ) | 2 | Ω | relevant ESR value at f = 10 kHz | 6 | ||
| Junction temperature (functional range) | Tj | -40 | 150 | °C | 6 | ||
| Output Voltage | VQ | 4.9 | 5 | 5.1 | V | 5 mA < IQ < 50 mA; 6 V < VI < 16 V | 7 |
| Output Voltage | VQ | 4.85 | 5 | 5.15 | V | 5 mA < IQ < 100 mA; 6 V < VI < 21 V | 7 |
| Output Voltage At Low Output Currents | VQ | 4.8 | 5 | 5.2 | V | 100 µA < IQ < 5 mA; 6 V < VI < 21 V | 7 |
| Dropout Voltage | Vdr | 220 | 500 | mV | IQ = 100 mA; Vdr = VI, VQ | 7 | |
| Load Regulation | ∆VQ, lo | 50 | 90 | mV | IQ = 1 mA to 100 mA; VI = 13.5 V | 7 | |
| Line Regulation | ∆VQ, li | 5 | 30 | mV | Vl = 6 V to 28 V; IQ = 1 mA | 7 | |
| Output Current Limitation | IQ | 150 | 200 | 500 | mA | VQ dropped 100 mV from nominal value obtained at VI = 13.5 V | 7 |
| Overtemperature Shutdown Threshold | Tj,sd | 151 | 200 | °C | Tj increasing | 7 | |
| Quiescent Current | Iq | 40 | 60 | µA | IQ = 100 µA, Tj < 85 °C | 7 | |
| Quiescent Current | Iq | 40 | 70 | µA | IQ = 100 µA | 7 | |
| Current Consumption | Iq | 1.7 | 4 | mA | IQ = 50 mA | 7 | |
| Junction to Case | RthJC | 17 | K/W | measured to heat slug | 6 | ||
| Junction to Ambient | RthJA | 54 | K/W | FR4 2s2p board | 6 | ||
| Junction to Ambient | RthJA | 139 | K/W | FR4 1s0p board, footprint only | 6 | ||
| Junction to Ambient | RthJA | 73 | K/W | FR4 1s0p board, 300 mm² heatsink area | 6 | ||
| Junction to Ambient | RthJA | 64 | K/W | FR4 1s0p board, 600 mm² heatsink area | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | ESD Absorption VESD,HBM -3, 3 kV Human Body | 5 |
CAD (KiCad official)
- Symbol:
TLE42644G - Footprint:
Package_TO_SOT_SMD:SOT-223 - 3D model: SOT-223-4 (KiCad packages3D, STEP)
- 3D model files:
tle42644g-etched.step/tle42644g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tle42644g.step/tle42644g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (15 pp, sha256
1d7d930f15a95e13, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TLE42644G
**Infineon Technologies** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223-4
TLE42644G from Infineon Technologies, in a SOT-223-4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | power_in | Input pin, rated for input voltage VI of 5.5 V to 40 V in the functional range (absolute maximum -30 V to 45 V), and should be blocked to ground directly at the IC with a ceramic capacitor (100 nF to 470 nF recommended). |
| 2 | GND | power_in | Ground reference for all voltages of the regulator, to be connected to the system ground. |
| 3 | Q | power_out | Regulated 5 V output (VQ,nom = 5 V, ±2 % up to 50 mA and ±3 % up to 100 mA), which must be blocked to ground with a capacitor of at least 10 µF with ESR below 2 Ω at 10 kHz placed close to the IC terminals. |
| 4 | GND | power_in | Ground connected internally to the leadframe and GND, which must be connected to GND and the heatsink area for thermal dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOT-223-4 |
| Category | Power Management (PMIC) |
| Pins | 4 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VI | -30 | | 45 | V | | 5 |
| Output voltage | VQ | -0.3 | | 32 | V | | 5 |
| Junction temperature | Tj | -40 | | 150 | °C | | 5 |
| Storage temperature | Tstg | -50 | | 150 | °C | | 5 |
| ESD Absorption | VESD,HBM | -3 | | 3 | kV | Human Body Model (HBM) | 5 |
| ESD Absorption | VESD,CDM | -1500 | | 1500 | V | Charge Device Model (CDM) at all pins | 5 |
| Input voltage | VI | 5.5 | | 40 | V | | 5 |
| Output Capacitor's Requirements for Stability | CQ | 10 | | | µF | | 5 |
| Output Capacitor's Requirements for Stability ESR | ESR(CQ) | | | 2 | Ω | relevant ESR value at f = 10 kHz | 6 |
| Junction temperature (functional range) | Tj | -40 | | 150 | °C | | 6 |
| Output Voltage | VQ | 4.9 | 5 | 5.1 | V | 5 mA < IQ < 50 mA; 6 V < VI < 16 V | 7 |
| Output Voltage | VQ | 4.85 | 5 | 5.15 | V | 5 mA < IQ < 100 mA; 6 V < VI < 21 V | 7 |
| Output Voltage At Low Output Currents | VQ | 4.8 | 5 | 5.2 | V | 100 µA < IQ < 5 mA; 6 V < VI < 21 V | 7 |
| Dropout Voltage | Vdr | | 220 | 500 | mV | IQ = 100 mA; Vdr = VI, VQ | 7 |
| Load Regulation | ∆VQ, lo | | 50 | 90 | mV | IQ = 1 mA to 100 mA; VI = 13.5 V | 7 |
| Line Regulation | ∆VQ, li | | 5 | 30 | mV | Vl = 6 V to 28 V; IQ = 1 mA | 7 |
| Output Current Limitation | IQ | 150 | 200 | 500 | mA | VQ dropped 100 mV from nominal value obtained at VI = 13.5 V | 7 |
| Overtemperature Shutdown Threshold | Tj,sd | 151 | | 200 | °C | Tj increasing | 7 |
| Quiescent Current | Iq | | 40 | 60 | µA | IQ = 100 µA, Tj < 85 °C | 7 |
| Quiescent Current | Iq | | 40 | 70 | µA | IQ = 100 µA | 7 |
| Current Consumption | Iq | | 1.7 | 4 | mA | IQ = 50 mA | 7 |
| Junction to Case | RthJC | | 17 | | K/W | measured to heat slug | 6 |
| Junction to Ambient | RthJA | | 54 | | K/W | FR4 2s2p board | 6 |
| Junction to Ambient | RthJA | | 139 | | K/W | FR4 1s0p board, footprint only | 6 |
| Junction to Ambient | RthJA | | 73 | | K/W | FR4 1s0p board, 300 mm² heatsink area | 6 |
| Junction to Ambient | RthJA | | 64 | | K/W | FR4 1s0p board, 600 mm² heatsink area | 6 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | | ESD Absorption VESD,HBM -3, 3 kV Human Body | 5 |
## CAD (KiCad official)
- Symbol: `TLE42644G`
- Footprint: `Package_TO_SOT_SMD:SOT-223`
- 3D model: SOT-223-4 (KiCad packages3D, STEP)
- 3D model files: `tle42644g-etched.step` / `tle42644g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tle42644g.step` / `tle42644g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Infineon Technologies datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588906218983198720) (15 pp, sha256 `1d7d930f15a95e13`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tle42644g-datasheet.pdf)