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TLE2027CDR

Public Made by Adom

by adom

Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLE2027CDR

Texas Instruments · Operational Amplifier · SOIC-8

TLE2027CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OFFSET N1 passive Offset null terminal 1 for trimming the input offset voltage; the datasheet gives no specific limit for this pin.
2 IN − input Inverting input of the operational amplifier; the datasheet gives no specific limit for this pin in this excerpt.
3 IN + input Non-inverting input of the operational amplifier; the datasheet gives no specific limit for this pin in this excerpt.
4 VCC − power_in Negative supply rail of the amplifier; the supply voltage limits are not stated in this excerpt.
5 OFFSET N2 passive Offset null terminal 2 for trimming the input offset voltage; the datasheet gives no specific limit for this pin.
6 OUT output Amplifier output; the datasheet gives no specific limit for this pin in this excerpt.
7 VCC + power_in Positive supply rail of the amplifier; the supply voltage limits are not stated in this excerpt.
8 NC unconnected No internal connection; the datasheet labels this pin NC and gives no further function.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 20 100 μV TA = 25°C 6
Input offset voltage (full range) VIO 145 μV TA = full range (0°C to 70°C) 6
Temperature coefficient of input offset voltage αVIO 0.4 1 μV/°C TA = full range (0°C to 70°C) 6
Input offset voltage long-term drift 0.006 1 μV/mo VIC = 0, RS = 50 Ω, TA = 25°C 6
Input offset current IIO 6 90 nA TA = 25°C 6
Input offset current (full range) IIO 150 nA TA = full range (0°C to 70°C) 6
Input bias current IIB 15 90 nA TA = 25°C 6
Input bias current (full range) IIB 150 nA TA = full range (0°C to 70°C) 6
Common-mode input voltage range VICR -11 11 V RS = 50 Ω, TA = 25°C 6
Common-mode input voltage range (full range) VICR -10.5 10.5 V RS = 50 Ω, TA = full range (0°C to 70°C) 6
Maximum positive peak output voltage swing VOM+ 10.5 12.9 V RL = 600 Ω, TA = 25°C 6
Maximum positive peak output voltage swing (full range) VOM+ 10 V RL = 600 Ω, TA = full range (0°C to 70°C) 6
Maximum positive peak output voltage swing VOM+ 12 13.2 V RL = 2 kΩ, TA = 25°C 6
Maximum positive peak output voltage swing (full range) VOM+ 11 V RL = 2 kΩ, TA = full range (0°C to 70°C) 6
Maximum negative peak output voltage swing VOM− -10.5 -13 V RL = 600 Ω, TA = 25°C 6
Maximum negative peak output voltage swing (full range) VOM− -10 V RL = 600 Ω, TA = full range (0°C to 70°C) 6
Maximum negative peak output voltage swing VOM− -12 -13.5 V RL = 2 kΩ, TA = 25°C 6
Maximum negative peak output voltage swing (full range) VOM− -11 V RL = 2 kΩ, TA = full range (0°C to 70°C) 6
Large-signal differential voltage amplification AVD 5 45 V/μV VO = ±11 V, RL = 2 kΩ, TA = 25°C 6
Large-signal differential voltage amplification (full range) AVD 2 V/μV VO = ±10 V, RL = 2 kΩ, TA = full range (0°C to 70°C) 6
Large-signal differential voltage amplification AVD 3.5 38 V/μV VO = ±10 V, RL = 1 kΩ, TA = 25°C 6
Large-signal differential voltage amplification (full range) AVD 1 V/μV VO = ±10 V, RL = 1 kΩ, TA = full range (0°C to 70°C) 6
Large-signal differential voltage amplification AVD 2 19 V/μV VO = ±10 V, RL = 600 Ω, TA = 25°C 6
Large-signal differential voltage amplification (full range) AVD 0.5 V/μV VO = ±10 V, RL = 600 Ω, TA = full range (0°C to 70°C) 6
Common-mode rejection ratio CMRR 100 131 dB VIC = VICRmin, TA = 25°C 6
Common-mode rejection ratio (full range) CMRR 98 dB VIC = VICRmin, RS = 50 Ω, TA = full range (0°C to 70°C) 6
Supply-voltage rejection ratio kSVR 94 144 dB VCC± = ±4 V to ±18 V, RS = 50 Ω, TA = 25°C 6
Supply-voltage rejection ratio (full range) kSVR 92 dB VCC± = ±4 V to ±18 V, RS = 50 Ω, TA = full range (0°C to 70°C) 6
Supply current ICC 3.8 5.3 mA VO = 0, No load, TA = 25°C 6
Supply current (full range) ICC 5.6 mA VO = 0, No load, TA = full range (0°C to 70°C) 6
Slew rate at unity gain SR 1.7 2.8 V/μs RL = 2 kΩ, CL = 100 pF, See Figure 1, TA = 25°C 7
Slew rate at unity gain (0°C to 70°C) SR 1.2 V/μs RL = 2 kΩ, CL = 100 pF, TA = 0°C to 70°C 7
Equivalent input noise voltage Vn 3.3 8 nV/√Hz RS = 20 Ω, f = 10 Hz 7
Equivalent input noise voltage Vn 2.5 4.5 nV/√Hz RS = 20 Ω, f = 1 kHz 7
Peak-to-peak equivalent input noise voltage VN(PP) 50 250 nV f = 0.1 Hz to 10 Hz 7
Equivalent input noise current In 10 25 pA/√Hz f = 10 Hz 7
Equivalent input noise current In 0.8 1.8 pA/√Hz f = 1 kHz 7
Total harmonic distortion THD 0.002 % VO = +10 V, AVD = 1, See Note 5 7
Unity-gain bandwidth B1 9 13 MHz RL = 2 kΩ, CL = 100 pF 7
Supply voltage VCC± 4 19 V C suffix 5
Common-mode input voltage VIC -11 11 V TA = 25°C 5
Common-mode input voltage VIC -10.5 10.5 V TA = full range (0°C to 70°C) 5
Operating free-air temperature TA 0 70 °C C suffix 5
Supply voltage, VCC+ VCC+ 19 V See Note 1 5
Supply voltage, VCC− VCC− -19 V 5
Differential input voltage VID -1.2 1.2 V See Note 2 5
Input current (each input) II -1 1 mA 5
Output current IO -50 50 mA 5
Total current into VCC+ 50 mA 5
Total current out of VCC− 50 mA 5
Storage temperature range Tstg -65 150 °C 5
Lead temperature, D package 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 5
Power rating, D package 725 mW TA ≤ 25°C 5
Power rating, D package 464 mW TA = 70°C 5
Derating factor, D package 5.8 mW/°C Above TA = 25°C 5

CAD (KiCad official)

  • Symbol: TLE2027CDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tle2027cdr-etched.step / tle2027cdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle2027cdr.step / tle2027cdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 aaef33067dba9367, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF