TLC7733QPWRQ1

Texas Instruments · Supervisor And Reset ICs · TSSOP-8

TLC7733QPWRQ1 from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CONTROL	input	Power-down control input: when tied to GND, RESET acts as active high; VIH is at least 0.7×VDD and VIL at most 0.2×VDD, with VIL kept below 0.3 V and VIH above VDD − 0.3 V for low supply current.
2	RESIN	input	Reset input whose logic levels are VIH at least 0.7×VDD and VIL at most 0.2×VDD, and which affects RESET/RESET outputs per the function table.
3	CT	passive	External timing capacitor pin that sets the reset delay as td = 2.1 × 10^4 × CT (CT in farads, td in seconds), giving td of 1.1 to 4.2 ms at CT = 100 nF.
4	GND	power_in	Ground reference; all voltage values in the datasheet are specified with respect to GND.
5	RESET	output	Totem-pole reset output (complement of pin 6 RESET) with maximum IOL of 10 mA and maximum IOH of −10 mA, recommended at 2 mA sink and −2 mA source; external pullup or pulldown is not required.
6	RESET	output	Totem-pole active-low reset output with maximum IOL of 10 mA and maximum IOH of −10 mA, recommended at 2 mA sink and −2 mA source; external pullup or pulldown is not required.
7	SENSE	input	Supply-monitor input compared against the TLC7733 negative-going threshold VIT− of 2.855 V to 3.03 V (typ 2.93 V) with 70 mV hysteresis; input voltage range is −0.3 V to 7 V.
8	VDD	power_in	Supply voltage input, recommended 2 V to 6 V (absolute maximum 7 V), with maximum supply current of 16 µA stated in the features.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-8
Category	Power Management (PMIC)
Pins	8

CAD (KiCad official)

Symbol: TLC7733QPWRQ1
Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
3D model: TSSOP-8 (KiCad packages3D, STEP)
3D model files: tlc7733qpwrq1-etched.step / tlc7733qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc7733qpwrq1.step / tlc7733qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (18 pp, sha256 2ae1799cef841b20, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TLC7733QPWRQ1

**Texas Instruments** · Supervisor And Reset ICs · TSSOP-8

TLC7733QPWRQ1 from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CONTROL | input | Power-down control input: when tied to GND, RESET acts as active high; VIH is at least 0.7×VDD and VIL at most 0.2×VDD, with VIL kept below 0.3 V and VIH above VDD − 0.3 V for low supply current. |
| 2 | RESIN | input | Reset input whose logic levels are VIH at least 0.7×VDD and VIL at most 0.2×VDD, and which affects RESET/RESET outputs per the function table. |
| 3 | CT | passive | External timing capacitor pin that sets the reset delay as td = 2.1 × 10^4 × CT (CT in farads, td in seconds), giving td of 1.1 to 4.2 ms at CT = 100 nF. |
| 4 | GND | power_in | Ground reference; all voltage values in the datasheet are specified with respect to GND. |
| 5 | RESET | output | Totem-pole reset output (complement of pin 6 RESET) with maximum IOL of 10 mA and maximum IOH of −10 mA, recommended at 2 mA sink and −2 mA source; external pullup or pulldown is not required. |
| 6 | RESET | output | Totem-pole active-low reset output with maximum IOL of 10 mA and maximum IOH of −10 mA, recommended at 2 mA sink and −2 mA source; external pullup or pulldown is not required. |
| 7 | SENSE | input | Supply-monitor input compared against the TLC7733 negative-going threshold VIT− of 2.855 V to 3.03 V (typ 2.93 V) with 70 mV hysteresis; input voltage range is −0.3 V to 7 V. |
| 8 | VDD | power_in | Supply voltage input, recommended 2 V to 6 V (absolute maximum 7 V), with maximum supply current of 16 µA stated in the features. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## CAD (KiCad official)

- Symbol: `TLC7733QPWRQ1`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `tlc7733qpwrq1-etched.step` / `tlc7733qpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc7733qpwrq1.step` / `tlc7733qpwrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](http://www.ti.com/cn/lit/gpn/tlc77-q1) (18 pp, sha256 `2ae1799cef841b20`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlc7733qpwrq1-datasheet.pdf)