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TLC7733QPWR
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TLC7733QPWR
Texas Instruments · Supervisor And Reset ICs · TSSOP-8
TLC7733QPWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CONTROL | input | Control input that, when tied to GND, makes RESET act as active high, and which is driven by the memory bank select signal for battery-backed SRAM control; keep VIL <0.3 V and VIH > VDD-0.3 V for low supply current. |
| 2 | RESIN | input | Reset input (active low) whose level, with CONTROL and SENSE, sets the RESET/RESET outputs per the function table; VIH min 0.7×VDD and VIL max 0.2×VDD. |
| 3 | CT | passive | Timing capacitor connection that sets the reset delay time td = 2.1 × 10^4 × CT (CT in farads, td in seconds). |
| 4 | GND | power_in | Ground reference for the device; all voltage values are with respect to GND. |
| 5 | RESET | output | Active-low totem-pole reset output (shown as overbar RESET on the pinout) that is asserted when SENSE is below the threshold and stays active until the delay td expires, with IOL up to 2 mA and IOH up to -2 mA recommended. |
| 6 | RESET | output | Active-high totem-pole reset output that is asserted when SENSE is below the threshold or per the function table, with IOL up to 2 mA and IOH up to -2 mA recommended. |
| 7 | SENSE | input | Voltage sense input monitored against the internal threshold (TLC7733 VIT- 2.86 V min, 2.93 V typ, 3 V max, with 70 mV hysteresis); input range 0 to VDD. |
| 8 | VDD | power_in | Supply voltage input, recommended 2 V to 6 V (absolute maximum 7 V), with RESET defined from VDD ≥ 1 V and a 0.1 µF bypass capacitor recommended near the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TLC7733QPWR - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
tlc7733qpwr-etched.step/tlc7733qpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc7733qpwr.step/tlc7733qpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
3147b2830d2531af, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TLC7733QPWR
**Texas Instruments** · Supervisor And Reset ICs · TSSOP-8
TLC7733QPWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CONTROL | input | Control input that, when tied to GND, makes RESET act as active high, and which is driven by the memory bank select signal for battery-backed SRAM control; keep VIL <0.3 V and VIH > VDD-0.3 V for low supply current. |
| 2 | RESIN | input | Reset input (active low) whose level, with CONTROL and SENSE, sets the RESET/RESET outputs per the function table; VIH min 0.7×VDD and VIL max 0.2×VDD. |
| 3 | CT | passive | Timing capacitor connection that sets the reset delay time td = 2.1 × 10^4 × CT (CT in farads, td in seconds). |
| 4 | GND | power_in | Ground reference for the device; all voltage values are with respect to GND. |
| 5 | RESET | output | Active-low totem-pole reset output (shown as overbar RESET on the pinout) that is asserted when SENSE is below the threshold and stays active until the delay td expires, with IOL up to 2 mA and IOH up to -2 mA recommended. |
| 6 | RESET | output | Active-high totem-pole reset output that is asserted when SENSE is below the threshold or per the function table, with IOL up to 2 mA and IOH up to -2 mA recommended. |
| 7 | SENSE | input | Voltage sense input monitored against the internal threshold (TLC7733 VIT- 2.86 V min, 2.93 V typ, 3 V max, with 70 mV hysteresis); input range 0 to VDD. |
| 8 | VDD | power_in | Supply voltage input, recommended 2 V to 6 V (absolute maximum 7 V), with RESET defined from VDD ≥ 1 V and a 0.1 µF bypass capacitor recommended near the pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TLC7733QPWR`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `tlc7733qpwr-etched.step` / `tlc7733qpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc7733qpwr.step` / `tlc7733qpwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlc77) (38 pp, sha256 `3147b2830d2531af`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tlc7733qpwr-datasheet.pdf)