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TLC7733QDR

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Texas Instruments Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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package.json tlc7733qdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 3d ago
page.json tlc7733qdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 3d ago
README.md Publish 0.1.0 · Ray 27d ago
tlc7733qdr-etched.glb tlc7733qdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 3d ago
tlc7733qdr-etched.step tlc7733qdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 3d ago
tlc7733qdr-hero.glb tlc7733qdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 3d ago
tlc7733qdr-hero.overlay.json tlc7733qdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray 3d ago
tlc7733qdr.glb Publish 0.1.0 · Ray 27d ago
tlc7733qdr.kicad_mod Publish 0.1.0 · Ray 27d ago
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TLC7733QDR

Texas Instruments · Supervisor And Reset ICs · SOIC-8

TLC7733QDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CONTROL input Control input for RESET/RESET logic, tied to the memory bank select for SRAM battery backup; input high level ≥0.7×VDD and low level ≤0.2×VDD.
2 RESIN input Active-low reset input that forces the reset outputs active; input high level ≥0.7×VDD and low level ≤0.2×VDD.
3 CT passive Delay-time capacitor connection; td = 2.1×10^4 × CT with CT in farads and td in seconds.
4 GND power_in Ground.
5 RESET output Active-low totem-pole reset output, active while SENSE is below threshold and during the delay time td.
6 RESET output Active-high totem-pole reset output, active while SENSE is below threshold and during the delay time td.
7 SENSE input Voltage sense input compared with the negative-going threshold VIT- (2.93 V typical for TLC7733); input range −0.3 V to 7 V.
8 VDD power_in Supply voltage, 2 V to 6 V recommended operating range, 7 V absolute maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: TLC7733QDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tlc7733qdr-etched.step / tlc7733qdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc7733qdr.step / tlc7733qdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 3147b2830d2531af, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF