component
TLC7725IDR
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# TLC7725IDR++**Texas Instruments** · Supervisor And Reset ICs · SOIC-8++TLC7725IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CONTROL | input | Control input for static-RAM power-down support, driven by the microprocessor memory bank select signal; VIH 0.7×VDD min, VIL 0.2×VDD max, and when tied to GND RESET acts as active high. |+| 2 | RESIN | input | Active-low reset input (RESIN); VIH 0.7×VDD min, VIL 0.2×VDD max, input current 2 µA max for VI = 0 V to VDD. |+| 3 | CT | passive | Connection for the external delay capacitor that sets the reset delay time td = 2.1 × 10^4 × CT (CT in farads, td in seconds). |+| 4 | GND | power_in | Ground reference for all voltages. |+| 5 | RESET | output | Active-low totem-pole reset output (overlined RESET), asserted when SENSE is below the threshold and held for delay time td after SENSE recovers. |+| 6 | RESET | output | Active-high totem-pole reset output (RESET), defined from VDD ≥ 1 V, with a 2 mA maximum recommended output current. |+| 7 | SENSE | input | Voltage-monitor input compared against the internal threshold; negative-going threshold for TLC7725 is 2.25 V typ (2.18 V to 2.32 V), hysteresis 70 mV, input range 0 to VDD. |+| 8 | VDD | power_in | Supply voltage input, recommended 2 V to 6 V (7 V absolute maximum), with a 0.1 µF ceramic bypass capacitor recommended near the supply terminal. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8 |+| Category | Power Management (PMIC) |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TLC7725IDR`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `tlc7725idr-etched.step` / `tlc7725idr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc7725idr.step` / `tlc7725idr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlc77) (38 pp, sha256 `3147b2830d2531af`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlc7725idr-datasheet.pdf)
page.jsonadded+201@@ -0,0 +1,201 @@+{+ "slug": "tlc7725idr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tlc7725idr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tlc7725idr.kicad_sym",+ "tlc7725idr.kicad_mod",+ "tlc7725idr.glb",+ "tlc7725idr.step",+ "tlc7725idr.lbr",+ "docs/hero.png",+ "docs/tlc7725idr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tlc7725idr-hero.glb",+ "tlc7725idr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TLC7725IDR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-8",+ "pin_count": 8,+ "category": "Power Management (PMIC)",+ "subcategory": "Supervisor And Reset ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tlc77",+ "parts": {+ "symbol": "tlc7725idr.kicad_sym",+ "footprint": "tlc7725idr.kicad_mod",+ "model_3d": "tlc7725idr-hero.glb",+ "model_3d_plain": "tlc7725idr.glb",+ "model_3d_step": "tlc7725idr-etched.step",+ "model_3d_step_plain": "tlc7725idr.step",+ "lbr": "tlc7725idr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2861112",+ "digikey": "TLC7725IDR-ND",+ "mouser": "595-TLC7725IDR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:19:04Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "TLC7725IDR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TLC7725IDR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CONTROL",+ "type": "input",+ "description": "Control input for static-RAM power-down support, driven by the microprocessor memory bank select signal; VIH 0.7×VDD min, VIL 0.2×VDD max, and when tied to GND RESET acts as active high."+ },+ {+ "number": "2",+ "name": "RESIN",+ "type": "input",+ "description": "Active-low reset input (RESIN); VIH 0.7×VDD min, VIL 0.2×VDD max, input current 2 µA max for VI = 0 V to VDD."+ },+ {+ "number": "3",+ "name": "CT",+ "type": "passive",+ "description": "Connection for the external delay capacitor that sets the reset delay time td = 2.1 × 10^4 × CT (CT in farads, td in seconds)."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for all voltages."+ },+ {+ "number": "5",+ "name": "RESET",+ "type": "output",+ "description": "Active-low totem-pole reset output (overlined RESET), asserted when SENSE is below the threshold and held for delay time td after SENSE recovers."+ },+ {+ "number": "6",+ "name": "RESET",+ "type": "output",+ "description": "Active-high totem-pole reset output (RESET), defined from VDD ≥ 1 V, with a 2 mA maximum recommended output current."+ },+ {+ "number": "7",+ "name": "SENSE",+ "type": "input",+ "description": "Voltage-monitor input compared against the internal threshold; negative-going threshold for TLC7725 is 2.25 V typ (2.18 V to 2.32 V), hysteresis 70 mV, input range 0 to VDD."+ },+ {+ "number": "8",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage input, recommended 2 V to 6 V (7 V absolute maximum), with a 0.1 µF ceramic bypass capacitor recommended near the supply terminal."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin 5 vs pin 6 RESET polarity was read from the overline in the top-view drawing on page 1 (pin 5 ov; TLC7725IDR was matched to the D (SOIC-8) package through the ordering table on page 17 (TLC7725IDR, ",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 38,+ "cost_usd": 0.8542,+ "at": "2026-10-08T16:18:42"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlc77",+ "pages": 38,+ "sha256": "3147b2830d2531af",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlc7725idr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlc7725idr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 4.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "2deb34113ea79b6640ee780222071b76492116014adbc3e65eebe783443aaa30",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}