component
TLC7705ID
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 26d ago |
| viewers | 26d ago |
| package.json | 3d ago |
| page.json | 3d ago |
| README.md | 26d ago |
| tlc7705id-etched.glb | 3d ago |
| tlc7705id-etched.step | 3d ago |
| tlc7705id-hero.glb | 3d ago |
| tlc7705id-hero.overlay.json | 3d ago |
| tlc7705id.glb | 26d ago |
| tlc7705id.kicad_mod | 26d ago |
| tlc7705id.kicad_sym | 26d ago |
| tlc7705id.lbr | 26d ago |
| tlc7705id.step | 26d ago |
TLC7705ID
Texas Instruments · Supervisor And Reset ICs · SOIC-8
TLC7705ID from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CONTROL | input | Control input for RAM power-down support; when tied to GND, RESET acts as active high, with logic levels VIH ≥ 0.7×VDD and VIL ≤ 0.2×VDD. |
| 2 | RESIN | input | Active-low reset input with VIH ≥ 0.7×VDD and VIL ≤ 0.2×VDD that forces the reset outputs active (see function table). |
| 3 | CT | passive | Connection for the external delay capacitor that sets the reset delay time td = 2.1 × 10^4 × CT (CT in farads, td in seconds). |
| 4 | GND | power_in | Ground reference; all voltage values are with respect to GND. |
| 5 | RESET | output | Active-low totem-pole reset output (overbar RESET on the pinout) that is asserted when SENSE is below the threshold or RESIN is low, and is defined from VDD ≥ 1 V. |
| 6 | RESET | output | Active-high totem-pole reset output that is asserted while SENSE is below the threshold, returning inactive after delay td. |
| 7 | SENSE | input | Voltage-sense input compared with the internal negative-going threshold (4.55 V typ for TLC7705, 4.47 to 4.63 V) with 70 mV hysteresis; input range -0.3 to 7 V. |
| 8 | VDD | power_in | Supply voltage input, recommended 2 V to 6 V (absolute max 7 V); a 0.1 µF ceramic bypass capacitor should be placed near the supply terminal. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TLC7705ID - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tlc7705id-etched.step/tlc7705id-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc7705id.step/tlc7705id.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
3147b2830d2531af, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).