component
TLC7628CDWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# TLC7628CDWR++**Texas Instruments** · Digital To Analog Converters (DACs) · SOIC-20-300mil++TLC7628CDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog ground terminal shared by both DACs (DACA and DACB), used as the ground reference for the analog outputs. |+| 2 | OUTA | output | DACA current output; output voltage to AGND is absolute-maximum rated at ±25 V. |+| 3 | RFBA | passive | DACA internal feedback resistor terminal for the external op-amp; feedback voltage to AGND is absolute-maximum rated at ±25 V. |+| 4 | REFA | input | DACA reference voltage input, specified for ±10 V with an input resistance of 5 to 20 kΩ to AGND. |+| 5 | DGND | power_in | Digital ground reference for the digital inputs; input voltage range is −0.3 V to VDD + 0.3 V referenced to DGND. |+| 6 | DACA/DACB | input | Control input that selects which DAC data latch (A or B) is loaded from the common 8-bit input port. |+| 7 | DB7 | input | Most significant bit (MSB) of the 8-bit data input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V. |+| 8 | DB6 | input | Data bit 6 of the 8-bit common input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V. |+| 9 | DB5 | input | Data bit 5 of the 8-bit common input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V. |+| 10 | DB4 | input | Data bit 4 of the 8-bit common input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V. |+| 11 | DB3 | input | Data bit 3 of the 8-bit common input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions. |+| 12 | DB2 | input | Data bit 2 of the 8-bit common input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions. |+| 13 | DB1 | input | Data bit 1 of the 8-bit common input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions. |+| 14 | DB0 | input | Least significant bit (LSB) of the 8-bit data input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions. |+| 15 | CS | input | Chip select; must be low for a write, with setup time 50 ns and hold time 0 ns, and when high the data inputs are disabled regardless of WR. |+| 16 | WR | input | Write strobe; pulse duration low minimum 50 ns, with CS and WR both low making the input latches transparent. |+| 17 | VDD | power_in | Positive supply, specified 10.8 V to 15.75 V and absolute-maximum rated at 17 V to AGND or DGND. |+| 18 | REFB | input | DACB reference voltage input, specified for ±10 V with an input resistance of 5 to 20 kΩ to AGND. |+| 19 | RFBB | passive | DACB internal feedback resistor terminal for the external op-amp; feedback voltage to AGND is absolute-maximum rated at ±25 V. |+| 20 | OUTB | output | DACB current output; output voltage to AGND is absolute-maximum rated at ±25 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | ADC/DAC/Data Conversion |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `TLC7628CDWR`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `tlc7628cdwr-etched.step` / `tlc7628cdwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc7628cdwr.step` / `tlc7628cdwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlc7628) (19 pp, sha256 `ab9617ace291fd3c`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlc7628cdwr-datasheet.pdf)
page.jsonadded+272@@ -0,0 +1,272 @@+{+ "slug": "tlc7628cdwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DACs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "tlc7628cdwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tlc7628cdwr.kicad_sym",+ "tlc7628cdwr.kicad_mod",+ "tlc7628cdwr.glb",+ "tlc7628cdwr.step",+ "tlc7628cdwr.lbr",+ "docs/hero.png",+ "docs/tlc7628cdwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tlc7628cdwr-hero.glb",+ "tlc7628cdwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TLC7628CDWR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-300mil",+ "pin_count": 20,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Digital To Analog Converters (DACs)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tlc7628",+ "parts": {+ "symbol": "tlc7628cdwr.kicad_sym",+ "footprint": "tlc7628cdwr.kicad_mod",+ "model_3d": "tlc7628cdwr-hero.glb",+ "model_3d_plain": "tlc7628cdwr.glb",+ "model_3d_step": "tlc7628cdwr-etched.step",+ "model_3d_step_plain": "tlc7628cdwr.step",+ "lbr": "tlc7628cdwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2679658",+ "digikey": "TLC7628CDWR-ND",+ "mouser": "595-TLC7628CDWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:16:04Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "TLC7628CDWR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TLC7628CDWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground terminal shared by both DACs (DACA and DACB), used as the ground reference for the analog outputs."+ },+ {+ "number": "2",+ "name": "OUTA",+ "type": "output",+ "description": "DACA current output; output voltage to AGND is absolute-maximum rated at ±25 V."+ },+ {+ "number": "3",+ "name": "RFBA",+ "type": "passive",+ "description": "DACA internal feedback resistor terminal for the external op-amp; feedback voltage to AGND is absolute-maximum rated at ±25 V."+ },+ {+ "number": "4",+ "name": "REFA",+ "type": "input",+ "description": "DACA reference voltage input, specified for ±10 V with an input resistance of 5 to 20 kΩ to AGND."+ },+ {+ "number": "5",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground reference for the digital inputs; input voltage range is −0.3 V to VDD + 0.3 V referenced to DGND."+ },+ {+ "number": "6",+ "name": "DACA/DACB",+ "type": "input",+ "description": "Control input that selects which DAC data latch (A or B) is loaded from the common 8-bit input port."+ },+ {+ "number": "7",+ "name": "DB7",+ "type": "input",+ "description": "Most significant bit (MSB) of the 8-bit data input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V."+ },+ {+ "number": "8",+ "name": "DB6",+ "type": "input",+ "description": "Data bit 6 of the 8-bit common input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V."+ },+ {+ "number": "9",+ "name": "DB5",+ "type": "input",+ "description": "Data bit 5 of the 8-bit common input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V."+ },+ {+ "number": "10",+ "name": "DB4",+ "type": "input",+ "description": "Data bit 4 of the 8-bit common input port; TTL-compatible with VIH minimum 2.4 V and VIL maximum 0.8 V."+ },+ {+ "number": "11",+ "name": "DB3",+ "type": "input",+ "description": "Data bit 3 of the 8-bit common input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions."+ },+ {+ "number": "12",+ "name": "DB2",+ "type": "input",+ "description": "Data bit 2 of the 8-bit common input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions."+ },+ {+ "number": "13",+ "name": "DB1",+ "type": "input",+ "description": "Data bit 1 of the 8-bit common input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions."+ },+ {+ "number": "14",+ "name": "DB0",+ "type": "input",+ "description": "Least significant bit (LSB) of the 8-bit data input port; setup time 25 ns and hold time 10 ns to WR per the recommended operating conditions."+ },+ {+ "number": "15",+ "name": "CS",+ "type": "input",+ "description": "Chip select; must be low for a write, with setup time 50 ns and hold time 0 ns, and when high the data inputs are disabled regardless of WR."+ },+ {+ "number": "16",+ "name": "WR",+ "type": "input",+ "description": "Write strobe; pulse duration low minimum 50 ns, with CS and WR both low making the input latches transparent."+ },+ {+ "number": "17",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply, specified 10.8 V to 15.75 V and absolute-maximum rated at 17 V to AGND or DGND."+ },+ {+ "number": "18",+ "name": "REFB",+ "type": "input",+ "description": "DACB reference voltage input, specified for ±10 V with an input resistance of 5 to 20 kΩ to AGND."+ },+ {+ "number": "19",+ "name": "RFBB",+ "type": "passive",+ "description": "DACB internal feedback resistor terminal for the external op-amp; feedback voltage to AGND is absolute-maximum rated at ±25 V."+ },+ {+ "number": "20",+ "name": "OUTB",+ "type": "output",+ "description": "DACB current output; output voltage to AGND is absolute-maximum rated at ±25 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin-to-function assignment was read from the TOP VIEW on page 1 (pins 1-10 left to right down, 20-11; The application schematics on pages 5-7 have garbled pin labels (e.g., VDD and DGND shown against nu"+ ],+ "pages_sent": 19,+ "cost_usd": 0.0871,+ "at": "2026-10-08T16:15:38"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlc7628",+ "pages": 19,+ "sha256": "ab9617ace291fd3c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlc7628cdwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlc7628cdwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7fd87b81ad98c3e33a1b1346eade23e41a262894ca8dca9df119abf9afc167f9",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}