component
TLC7528CDWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), SOIC-20-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLC7528CDWR
Texas Instruments · Digital To Analog Converters (DAC) · SOIC-20-300mil
TLC7528CDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground reference shared by DACA and DACB R-2R ladder networks (terminal 1). |
| 2 | OUTA | output | DACA current output summing the R-2R ladder current to AGND; output leakage current up to ±400nA max (VDD=5V, latch=00000000). |
| 3 | RFBA | passive | DACA on-chip feedback resistor terminal, normally connected to an external op-amp output for current-to-voltage conversion; feedback voltage rated ±25V to AGND. |
| 4 | REFA | input | Reference voltage input for DACA; recommended ±10V, absolute maximum ±25V to AGND. |
| 5 | DGND | power_in | Digital ground reference for the input logic and data latch circuitry. |
| 6 | DACA/DACB | input | DAC-select control input: low level directs a write to the DACA latch, high level directs a write to the DACB latch, active only while CS and WR are both low. |
| 7 | DB7 | input | Most significant bit (MSB) of the 8-bit parallel data input bus, TTL-compatible at VDD=5V, data setup time 25ns min. |
| 8 | DB6 | input | Data bit 6 of the 8-bit parallel data input bus. |
| 9 | DB5 | input | Data bit 5 of the 8-bit parallel data input bus. |
| 10 | DB4 | input | Data bit 4 of the 8-bit parallel data input bus. |
| 11 | DB3 | input | Data bit 3 of the 8-bit parallel data input bus. |
| 12 | DB2 | input | Data bit 2 of the 8-bit parallel data input bus. |
| 13 | DB1 | input | Data bit 1 of the 8-bit parallel data input bus. |
| 14 | DB0 | input | Least significant bit (LSB) of the 8-bit parallel data input bus. |
| 15 | CS | input | Chip-select input; must be low together with WR to enable a write to the selected DAC latch, setup time tsu(CS)=50ns min, hold time th(CS)=0ns min. |
| 16 | WR | input | Write strobe input; the addressed DAC latch becomes transparent when WR and CS are both low and latches data when either goes high, minimum WR-low pulse duration tw(WR)=50ns. |
| 17 | VDD | power_in | Positive supply voltage, operating range 5V to 15V (recommended 4.75V-5.25V or 14.5V-15.5V), absolute maximum -0.3V to 16.5V referenced to AGND/DGND. |
| 18 | REFB | input | Reference voltage input for DACB; recommended ±10V, absolute maximum ±25V to AGND. |
| 19 | RFBB | passive | DACB on-chip feedback resistor terminal, normally connected to an external op-amp output for current-to-voltage conversion; feedback voltage rated ±25V to AGND. |
| 20 | OUTB | output | DACB current output summing the R-2R ladder current to AGND; output leakage current up to ±400nA max (VDD=5V, latch=00000000). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Data Acquisition |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
TLC7528CDWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
tlc7528cdwr-etched.step/tlc7528cdwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc7528cdwr.step/tlc7528cdwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
63cd9d470d8a8f3e, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).