component
TLC7524ED
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DAC), SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLC7524ED
Texas Instruments · Digital To Analog Converters (DAC) · SOIC-16
TLC7524ED from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | DAC current output 1, to which the binary-weighted ladder currents are switched; in voltage-mode operation a fixed input voltage is placed here and the analog output voltage appears at REF. |
| 2 | OUT2 | output | DAC current output 2, which receives the entire reference current when all digital inputs are low; the datasheet test conditions hold OUT1 and OUT2 at GND unless otherwise noted. |
| 3 | GND | power_in | Device ground and common reference for the DAC, as used in the test conditions and circuit configurations. |
| 4 | DB7 | input | Data input bit 7, the most significant bit (MSB) of the 8-bit digital input word, latched while CS or WR is high. |
| 5 | DB6 | input | Data input bit 6 of the 8-bit digital input word, latched while CS or WR is high. |
| 6 | DB5 | input | Data input bit 5 of the 8-bit digital input word, latched while CS or WR is high. |
| 7 | DB4 | input | Data input bit 4 of the 8-bit digital input word, latched while CS or WR is high. |
| 8 | DB3 | input | Data input bit 3 of the 8-bit digital input word, latched while CS or WR is high. |
| 9 | DB2 | input | Data input bit 2 of the 8-bit digital input word, latched while CS or WR is high. |
| 10 | DB1 | input | Data input bit 1 of the 8-bit digital input word, latched while CS or WR is high. |
| 11 | DB0 | input | Data input bit 0, the least significant bit (LSB) of the 8-bit digital input word, latched while CS or WR is high. |
| 12 | CS | input | Chip select, active low; with CS and WR both low the input latches are transparent, and with CS high the data inputs are disabled regardless of WR; CS setup time is 40 ns minimum and hold time 0 ns minimum. |
| 13 | WR | input | Write input, active low; its low pulse duration must be at least 40 ns, and data on DB0-DB7 is latched when WR or CS goes high. |
| 14 | VDD | power_in | Positive single supply for the device, specified from 5 V to 15 V (recommended 4.75-5.25 V at 5 V nominal and 14.5-15.5 V at 15 V nominal; absolute maximum 16.5 V). |
| 15 | REF | input | Reference voltage input to the DAC ladder, recommended Vref ±10 V (absolute maximum ±25 V), with a reference input impedance of 5 kΩ to 20 kΩ to GND. |
| 16 | RFB | passive | Terminal of the internal feedback resistor, connected to the external operational amplifier output in the unipolar and bipolar circuits shown; gain error is measured using this internal resistor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Data Acquisition |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
TLC7524ED - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
tlc7524ed-etched.step/tlc7524ed-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc7524ed.step/tlc7524ed.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
ce7ba0309086b44c, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).