component
TLC7524CN
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| viewers | 4d ago |
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| tlc7524cn-etched.glb | 4d ago |
| tlc7524cn-etched.step | 4d ago |
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TLC7524CN
Texas Instruments · Digital To Analog Converters (DACs) · PDIP-16
TLC7524CN from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Current output terminal of the DAC whose on-state switch capacitance is up to 120pF depending on the digital input code. |
| 2 | OUT2 | output | Complementary current output terminal of the DAC whose off-state switch capacitance is up to 30pF with all digital inputs high. |
| 3 | GND | power_in | Ground reference for the device, to which OUT1 and OUT2 are held during electrical characterization. |
| 4 | DB7 | input | Most significant digital data input bit (MSB) of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 5 | DB6 | input | Digital data input bit 6 of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 6 | DB5 | input | Digital data input bit 5 of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 7 | DB4 | input | Digital data input bit 4 of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 8 | DB3 | input | Digital data input bit 3 of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 9 | DB2 | input | Digital data input bit 2 of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 10 | DB1 | input | Digital data input bit 1 of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 11 | DB0 | input | Least significant digital data input bit (LSB) of the 8-bit parallel data bus, with VIH of at least 2.4V and VIL of at most 0.8V at VDD = 5V. |
| 12 | CS | input | Chip select input; when high the data inputs are disabled regardless of WR, and CS setup time before a write is 40ns minimum. |
| 13 | WR | input | Write input; when CS and WR are both low the input latches are transparent, and the WR low pulse duration must be at least 40ns. |
| 14 | VDD | power_in | Positive supply operating from 5V to 15V single supply, with an absolute maximum of 16.5V. |
| 15 | REF | input | Reference voltage input Vref, rated ±10V in recommended operation and ±25V absolute maximum, with a 5 to 20 kΩ input impedance to GND. |
| 16 | RFB | passive | Terminal of the internal feedback resistor used to set the output gain, measured for gain error with this internal resistor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 4.75 | 5 | 5.25 | V | VDD = 5V | 3 |
| Supply voltage | VDD | 14.5 | 15 | 15.5 | V | VDD = 15V | 3 |
| Reference voltage | Vref | -10 | 10 | V | VDD = 5V | 3 | |
| High-level input voltage | VIH | 2.4 | V | VDD = 5V | 3 | ||
| High-level input voltage | VIH | 13.5 | V | VDD = 15V | 3 | ||
| Low-level input voltage | VIL | 0.8 | V | VDD = 5V | 3 | ||
| Low-level input voltage | VIL | 1.5 | V | VDD = 15V | 3 | ||
| CS setup time | tsu(CS) | 40 | ns | 3 | |||
| CS hold time | th(CS) | 0 | ns | 3 | |||
| Data bus input setup time | tsu(D) | 25 | ns | 3 | |||
| Data bus input hold time | th(D) | 10 | ns | 3 | |||
| Pulse duration, WR low | tw(WR) | 40 | ns | 3 | |||
| Operating free-air temperature | TA | 0 | 70 | °C | TLC7524C | 3 | |
| Supply voltage range | VDD | -0.3 | 16.5 | V | 2 | ||
| Digital input voltage range | VI | -0.3 | V | upper limit VDD + 0.3V | 2 | ||
| Reference voltage | Vref | -25 | 25 | V | 2 | ||
| Peak digital input current | II | 10 | µA | 2 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| Lead temperature | 260 | °C | 1,6mm (1/16 inch) from case for 10 seconds, D, N, or PW package | 2 | |||
| High-level input current | IIH | 10 | µA | VI = VDD | 3 | ||
| Low-level input current | IIL | -10 | µA | VI = 0 | 3 | ||
| Output leakage current OUT1 | IIkg | -400 | 400 | nA | OUT1 DB0−DB7 at 0V, Vref = ±10V, WR, CS at 0V; VDD = 5V | 3 | |
| Output leakage current OUT1 | IIkg | -200 | 200 | nA | OUT1 DB0−DB7 at 0V, Vref = ±10V, WR, CS at 0V; VDD = 15V | 3 | |
| Output leakage current OUT2 | IIkg | -400 | 400 | nA | OUT2 DB0−DB7 at VDD, Vref = ±10V, WR, CS at 0V; VDD = 5V | 3 | |
| Output leakage current OUT2 | IIkg | -200 | 200 | nA | OUT2 DB0−DB7 at VDD, Vref = ±10V, WR, CS at 0V; VDD = 15V | 3 | |
| Supply current Quiescent | IDD | 1 | 2 | mA | DB0−DB7 at VIHmin or VILmax | 3 | |
| Supply current Standby | IDD | 500 | µA | DB0−DB7 at 0V or VDD | 3 | ||
| Supply voltage sensitivity, ∆gain/∆VDD | kSVS | 0.01 | 0.16 | %FSR/% | ∆VDD = ±10%; VDD = 5V | 3 | |
| Supply voltage sensitivity, ∆gain/∆VDD | kSVS | 0.005 | 0.04 | %FSR/% | ∆VDD = ±10%; VDD = 15V | 3 | |
| Input capacitance | Ci | 5 | pF | DB0−DB7, WR, CS; VI = 0 | 3 | ||
| Output capacitance OUT1 | Co | 30 | pF | OUT1 DB0−DB7 at 0V, WR, CS at 0V | 3 | ||
| Output capacitance OUT2 | Co | 120 | pF | OUT2 DB0−DB7 at 0V, WR, CS at 0V | 3 | ||
| Output capacitance OUT1 | Co | 120 | pF | OUT1 DB0−DB7 at VDD, WR, CS at 0V | 3 | ||
| Output capacitance OUT2 | Co | 30 | pF | OUT2 DB0−DB7 at VDD, WR, CS at 0V | 3 | ||
| Reference input impedance (REF to GND) | 5 | 20 | kΩ | VDD = 5V | 3 | ||
| Linearity error | -0.5 | 0.5 | LSB | 4 | |||
| Gain error | -2.5 | 2.5 | LSB | See Note 1 | 4 | ||
| Settling time (to 1/2 LSB) | 100 | ns | See Note 2 | 4 | |||
| Propagation delay from digital input to 90% of final analog output current | 80 | ns | See Note 2 | 4 | |||
| Feedthrough at OUT1 or OUT2 | 0.5 | %FSR | Vref = ±10V (100kHz sinewave); WR and CS at 0V, DB0−DB7 at 0V | 4 | |||
| Temperature coefficient of gain | -0.004 | 0.004 | %FSR/°C | TA = +25°C to MAX; VDD = 5V | 4 | ||
| Temperature coefficient of gain | -0.001 | 0.001 | %FSR/°C | TA = +25°C to MAX; VDD = 15V | 4 | ||
| Linearity error at REF | 1 | LSB | VDD = 5V, OUT1 = 2.5V, OUT2 at GND, TA = +25°C | 5 |
CAD (KiCad official)
- Symbol:
TLC7524CN - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
tlc7524cn-etched.step/tlc7524cn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc7524cn.step/tlc7524cn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
ce7ba0309086b44c, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).