component

TLC7135CDWR

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitiontlc7135cdwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

TLC7135CDWR

Texas Instruments · Analog To Digital Converters (ADC) · SOIC-28-300mil

TLC7135CDWR from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC− power_in Negative supply voltage connection, typically −5 V for dual-supply operation.
2 REF input Reference voltage input, typically 1 V, used for A/D conversion timing and scale factor.
3 ANLG COMMON power_in Analog common/ground point, internally connected to IN− during auto-zero, deintegrate, and zero integrator phases.
4 INT OUT output Integrator output for external ramp monitoring or compensation via rollover resistor and diode.
5 AUTO ZERO passive Auto-zero capacitor terminal, connected to external auto-zero capacitor (typical 1 µF) for offset voltage compensation.
6 BUFF OUT output Buffer amplifier output from the differential input stage.
7 Cref− passive Reference capacitor negative terminal, connected to external reference capacitor (typical 1 µF) for integrator timing.
8 Cref+ passive Reference capacitor positive terminal, connected to external reference capacitor.
9 IN− input Negative differential input terminal, can be tied to ANLG COMMON for single-ended operation, maximum ±2 V from ANLG COMMON.
10 IN+ input Positive differential input terminal, accepts analog input signal, maximum ±2 V from ANLG COMMON.
11 VCC+ power_in Positive supply voltage connection, typically +5 V for dual-supply operation.
12 D5 output Most significant digit (MSD) drive output, goes high for 200 clock pulses sequentially to drive display digit drivers.
13 B1 output Binary-coded-decimal least significant bit (LSB) output for digital display decoder interface.
14 B2 output Binary-coded-decimal output bit for digital display decoder interface.
15 B4 output Binary-coded-decimal output bit for digital display decoder interface.
16 B8 output Binary-coded-decimal most significant bit (MSB) output for digital display decoder interface.
17 D4 output Digit drive output for second least significant digit, goes high for 200 clock pulses sequentially.
18 D3 output Digit drive output for middle digit, goes high for 200 clock pulses sequentially.
19 D2 output Digit drive output for second most significant digit, goes high for 200 clock pulses sequentially.
20 D1 output Least significant digit (LSD) drive output, goes high for 200 clock pulses sequentially.
21 BUSY output Busy output, goes high at beginning of signal integrate phase and remains high until first clock pulse after zero crossing or end of measurement cycle on over-range condition.
22 CLK input Clock input, sets conversion speed and measurement cycle timing, recommended operating frequency 120 kHz, maximum 2 MHz.
23 POLARITY output Polarity output, goes high for positive input signal and updates at beginning of each deintegrate phase.
24 DGTL GND power_in Digital ground connection, separate from analog common to minimize noise coupling between digital and analog sections.
25 RUN/HOLD input Run/Hold control input, high or open causes continuous measurement cycles every 40,002 clock pulses, low holds conversion reading until positive pulse initiates new cycle.
26 STROBE input Strobe input for external data latching, negative-going pulses transfer multiplexed BCD conversion data to external latches or microprocessors.
27 OVER RANGE output Over-range output, goes high when input voltage magnitude exceeds ±2 V (for 1 V reference) or ±99,999 count equivalent.
28 UNDER RANGE output Under-range output, goes high when conversion result is ≤9% of full-scale range (count ≤1800), indicating low signal magnitude.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-28-300mil
Category Data Acquisition
Pins 28

CAD (KiCad official)

  • Symbol: TLC7135CDWR
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: tlc7135cdwr-etched.step / tlc7135cdwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc7135cdwr.step / tlc7135cdwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 89de1bb2c0ac6ea0, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF