# TLC5620IDR

**Texas Instruments** · Digital To Analog Converters (DAC) · SOIC-14

TLC5620IDR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground return and reference terminal for the device; the resistor strings of all four DACs are tied to this terminal. |
| 2 | REFA | input | Reference voltage input to DAC A that defines its output analog range; the input is buffered and high impedance, and Vref is specified as VDD-1.5 V maximum. |
| 3 | REFB | input | Reference voltage input to DAC B that defines its output analog range; the input is buffered and high impedance, and Vref is specified as VDD-1.5 V maximum. |
| 4 | REFC | input | Reference voltage input to DAC C that defines its output analog range; the input is buffered and high impedance, and Vref is specified as VDD-1.5 V maximum. |
| 5 | REFD | input | Reference voltage input to DAC D that defines its output analog range; the input is buffered and high impedance, and Vref is specified as VDD-1.5 V maximum. |
| 6 | DATA | input | Serial interface digital data input; the DAC code is clocked into the serial register MSB first, with each bit captured on the falling edge of CLK. |
| 7 | CLK | input | Serial interface clock; input data is shifted into the serial interface register on the falling edge of CLK, with a maximum frequency of 1 MHz. |
| 8 | LOAD | input | Serial interface load control; when LDAC is low, the falling edge of LOAD latches the data into the output latch and immediately produces the analog voltage at the DAC output, with a minimum LOAD pulse width of 250 ns. |
| 9 | DACD | output | DAC D analog output, buffered with a configurable x1 or x2 gain output range. |
| 10 | DACC | output | DAC C analog output, buffered with a configurable x1 or x2 gain output range. |
| 11 | DACB | output | DAC B analog output, buffered with a configurable x1 or x2 gain output range. |
| 12 | DACA | output | DAC A analog output, buffered with a configurable x1 or x2 gain output range. |
| 13 | LDAC | input | Load DAC control; when high, no DAC output updates occur as input data is read into the serial register, and the DAC outputs update only on a high-to-low LDAC transition. |
| 14 | VDD | power_in | Positive supply voltage, specified at 4.75 V to 5.25 V (5 V ±5%) in the recommended operating conditions. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Data Acquisition |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `TLC5620IDR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `tlc5620idr-etched.step` / `tlc5620idr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc5620idr.step` / `tlc5620idr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlc5620.pdf) (18 pp, sha256 `9ce88ae341deb373`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlc5620idr-datasheet.pdf)