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TLC5615CN

Public Made by Adom

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HGSEMI Digital To Analog Converters (DAC), DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLC5615CN

HGSEMI · Digital To Analog Converters (DAC) · DIP-8

TLC5615CN from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN input Serial data input that receives the 16-bit data word, with VIH of 2.4 V minimum and VIL of 0.8 V maximum, and a DIN setup time of 45 ns before SCLK high.
2 SCLK input Serial clock input, which should be held low while CS is high to minimize clock feedthrough, with VIH of 2.4 V minimum and VIL of 0.8 V maximum.
3 CS input Active-low chip select input, with VIH of 2.4 V minimum, VIL of 0.8 V maximum, and a minimum CS high pulse width of 20 ns.
4 DOUT output Serial data output for daisy chaining, with VOH of VDD-1 V minimum at IO = -2 mA, VOL of 0.4 V maximum at IO = 2 mA, and a propagation delay of 50 ns maximum at CL = 50 pF.
5 AGND power_in Analog ground reference for the DAC, with the device rated for a supply of VDD to AGND of 7 V absolute maximum.
6 REFIN input High-impedance buffered reference input whose recommended voltage is 2 V to VDD-2 V, with an input voltage range of 0 to VDD-2 V and input resistance of 10 MΩ.
7 OUT output DAC analog voltage output with a range of 0 to VDD-0.4 V at RL = 10 kΩ, a recommended minimum load of 2 kΩ, and a short-circuit current of 20 mA to VDD or AGND.
8 VDD power_in Positive power supply, specified at 4.5 V to 5.5 V (5 V nominal) with an absolute maximum of 7 V to AGND.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-8
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VDD VDD 4.5 5 5.5 V 4
High-level digital input voltage VIH 2.4 V 4
Low-level digital input voltage VIL 0.8 V 4
Reference voltage, Vref to REFIN terminal Vref 2 2.048 V to REFIN terminal 4
Operating free-air temperature, TA (TLC5615C) TA 0 70 ℃ TLC5615C 4
Supply voltage (VDD to AGND) VDD 7 V 4
Digital input voltage range to AGND -0.3 V 4
Reference input voltage range to AGND -0.3 V 4
Continuous current at any terminal -20 20 mA 4
Storage temperature range Tstg -65 150 ℃ 4
Lead temperature 260 ℃ 1,6 mm (1/16 inch) from the case for 10 seconds 4
Integral nonlinearity, end point adjusted (INL) INL -1 1 LSB Vref = 2.048 V, See Note 1 4
Differential nonlinearity (DNL) DNL -0.5 0.1 0.5 LSB Vref = 2.048 V, See Note 2 4
Zero-scale error (offset error at zero scale) EZS -3 3 LSB Vref = 2.048 V, See Note 3 4
Gain error EG -3 3 LSB Vref = 2.048 V, See Note 5 4
Power-supply rejection ratio, zero scale PSRR 80 dB Zero scale, See Notes 7 and 8 4
Power-supply rejection ratio, gain PSRR 80 dB Gain, See Notes 7 and 8 4
Voltage output range VO 0 V RL = 10 kΩ 5
Output load regulation accuracy 0.5 LSB VO(OUT) = 2 V, RL = 2 kΩ 5
Output short circuit current IOSC 20 mA OUT to VDD or AGND 5
Output voltage, low-level VOL(low) 0.25 V IO(OUT) ≤ 5 mA 5
Output voltage, high-level VOH(high) 4.75 V IO(OUT) ≤ -5 mA 5
Reference input voltage VI 0 V 5
Input resistance (REFIN) ri 10 MΩ 5
Input voltage (REFIN) high-level digital input voltage VIH 2.4 V 5
Low-level digital input voltage VIL 0.8 V 5
High-level digital input current IIH -1 1 µA VI = VDD 5
Low-level digital input current IIL -1 1 µA VI = 0 5
Output voltage, low-level (DOUT) VOL 0.4 V IO = 2 mA 5
Supply voltage VDD 4.5 5 5.5 V 6
Power supply current, Vref = 0 IDD 150 250 µA VDD = 5.5 V, No load, All inputs = 0 V or VDD, Vref = 0 6
Power supply current, Vref = 2.048 V IDD 230 350 µA VDD = 5.5 V, No load, All inputs = 0 V or VDD, Vref = 2.048 V 6
Signal-to-noise + distortion, S/(N+D) S/(N+D) 60 dB Vref = 1 Vpp at 1 kHz + 2.048 Vdc, code = 11 1111 1111, See Note 9 6
Setup time, DIN before SCLK high tsu(DS) 45 ns 6
Hold time, DIN valid after SCLK high th(DH) 0 ns 6
Setup time, CS low to SCLK high tsu(CSS) 1 ns 6
Setup time, CS high to SCLK high tsu(CS1) 50 ns 6
Hold time, SCLK low to CS low th(CSH0) 1 ns 6
Hold time, SCLK low to CS high th(CSH1) 0 ns 6
Pulse duration, minimum chip select pulse width high tw(CS) 20 ns 6
Pulse duration, SCLK low tw(CL) 25 ns 6
Pulse duration, SCLK high tw(CH) 25 ns 6
Propagation delay time, DOUT tpd(DOUT) 50 ns CL = 50 pF 6
Output slew rate SR 0.3 0.5 V/µs CL = 100 pF, TA = 25℃, RL = 10 kΩ 7
Output settling time to 0.5 LSB ts 12.5 µs To 0.5 LSB, RL = 10 kΩ, CL = 100 pF, See Note 10 7
Glitch energy 5 Nv·s DIN = All 0s to all 1s 7
Reference feedthrough -80 dB REFIN = 1 Vpp at 1 kHz + 2.048 Vdc, See Note 11 7
Zero-scale-error temperature coefficient EZS TC 3 ppm/℃ Vref = 2.048 V, See Note 4 4
Gain-error temperature coefficient EG TC 1 ppm/℃ Vref = 2.048 V, See Note 6 4
Input capacitance (REFIN) Ci 5 pF 5
Input capacitance (digital inputs) Ci 8 pF 5

CAD (KiCad official)

  • Symbol: TLC5615CN
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: DIP-8 (KiCad packages3D, STEP)
  • 3D model files: tlc5615cn-etched.step / tlc5615cn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc5615cn.step / tlc5615cn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (11 pp, sha256 660a24dd5f191c62, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF