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TLC5540IPWR

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLC5540IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-24

TLC5540IPWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable: when OE is low the D1-D8 data outputs are enabled, and when OE is high D1-D8 are high impedance.
2 DGND power_in Digital ground; the datasheet requires AGND−DGND to remain within −100 mV to 100 mV.
3 D1 output Digital data output bit 1, the LSB (D1 is the least significant bit).
4 D2 output Digital data output bit 2 of the 8-bit conversion result.
5 D3 output Digital data output bit 3 of the 8-bit conversion result.
6 D4 output Digital data output bit 4 of the 8-bit conversion result.
7 D5 output Digital data output bit 5 of the 8-bit conversion result.
8 D6 output Digital data output bit 6 of the 8-bit conversion result.
9 D7 output Digital data output bit 7 of the 8-bit conversion result.
10 D8 output Digital data output bit 8, the MSB (D8 is the most significant bit).
11 VDDD power_in Digital supply; VDDD−AGND must be within 4.75 V to 5.25 V (5 V nominal).
12 CLK input Conversion clock input; clock high and clock low pulse durations must each be at least 12.5 ns.
13 VDDD power_in Digital supply; VDDD−AGND must be within 4.75 V to 5.25 V (5 V nominal).
14 VDDA power_in Analog supply; VDDA−AGND must be within 4.75 V to 5.25 V (5 V nominal).
15 VDDA power_in Analog supply; VDDA−AGND must be within 4.75 V to 5.25 V (5 V nominal).
16 REFTS passive Top reference sense terminal; when using the internal divider it is shorted to REFT (and REFBS to REFB) to generate a nominal 2 V reference.
17 REFT input Top reference voltage input; it must be at least 1.8 V above REFB and no higher than VDDA.
18 VDDA power_in Analog supply; VDDA−AGND must be within 4.75 V to 5.25 V (5 V nominal).
19 ANALOG IN input Analog input; the input range is bounded by REFB (minimum) and REFT (maximum), and the source impedance should be less than 100 Ω.
20 AGND power_in Analog ground; connect directly to the analog ground plane.
21 AGND power_in Analog ground; connect directly to the analog ground plane.
22 REFBS passive Bottom reference sense terminal; when using the internal divider it is shorted to REFB (and REFTS to REFT) to generate a nominal 2 V reference.
23 REFB input Bottom reference voltage input; it must be between 0 V and REFT−1.8 V.
24 DGND power_in Digital ground; connect directly to the analog ground plane to avoid a ground loop.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Data Acquisition
Pins 24

CAD (KiCad official)

  • Symbol: TLC5540IPWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: tlc5540ipwr-etched.step / tlc5540ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc5540ipwr.step / tlc5540ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 d699433f8d86077c, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF