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TLC5510IPWR

Public Made by Adom

by adom

Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLC5510IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-24

TLC5510IPWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable: when OE is low the data outputs D1-D8 are enabled, and when OE is high D1-D8 are in the high-impedance state.
2 DGND power_in Digital ground; AGND and DGND are connected internally, so AGND-DGND must stay within -100 mV to 100 mV.
3 D1 output Digital data output, D1 is the LSB of the 8-bit output code.
4 D2 output Digital data output bit 2 of the 8-bit output code.
5 D3 output Digital data output bit 3 of the 8-bit output code.
6 D4 output Digital data output bit 4 of the 8-bit output code.
7 D5 output Digital data output bit 5 of the 8-bit output code.
8 D6 output Digital data output bit 6 of the 8-bit output code.
9 D7 output Digital data output bit 7 of the 8-bit output code.
10 D8 output Digital data output, D8 is the MSB of the 8-bit output code.
11 VDDD power_in Digital supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to DGND.
12 CLK input Clock input; high and low pulse durations must each be at least 25 ns, with VIH at least 4 V and VIL at most 1 V.
13 VDDD power_in Digital supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to DGND.
14 VDDA power_in Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND.
15 VDDA power_in Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND.
16 REFTS passive Top reference sense: shorted to REFT for the TLC5510 2-V internal divider configuration, and connected to VDDA for the TLC5510A 4-V configuration.
17 REFT input Top reference voltage; for the TLC5510A it must be at least VREFB + 2 V and at most 4 V.
18 VDDA power_in Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND.
19 ANALOG IN input Analog input whose range is VREFB to VREFT; the driving source resistance should be 10 Ω or less within the frequency range of interest.
20 AGND power_in Analog ground, to be tied to the analog ground plane.
21 AGND power_in Analog ground, to be tied to the analog ground plane.
22 REFBS passive Bottom reference sense: shorted to REFB for the TLC5510 2-V internal divider configuration, and connected to ground for the TLC5510A 4-V configuration.
23 REFB input Bottom reference voltage; for the TLC5510A it must be at least 0 V and at most VREFT - 4 V.
24 DGND power_in Digital ground; AGND and DGND are connected internally, so AGND-DGND must stay within -100 mV to 100 mV.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Data Acquisition
Pins 24

CAD (KiCad official)

  • Symbol: TLC5510IPWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: tlc5510ipwr-etched.step / tlc5510ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc5510ipwr.step / tlc5510ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 342cbda59fa98fd6, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF