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TLC5510IPWR
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Texas Instruments Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# TLC5510IPWR++**Texas Instruments** · Analog To Digital Converters (ADC) · TSSOP-24++TLC5510IPWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Output enable: when OE is low the data outputs D1-D8 are enabled, and when OE is high D1-D8 are in the high-impedance state. |+| 2 | DGND | power_in | Digital ground; AGND and DGND are connected internally, so AGND-DGND must stay within -100 mV to 100 mV. |+| 3 | D1 | output | Digital data output, D1 is the LSB of the 8-bit output code. |+| 4 | D2 | output | Digital data output bit 2 of the 8-bit output code. |+| 5 | D3 | output | Digital data output bit 3 of the 8-bit output code. |+| 6 | D4 | output | Digital data output bit 4 of the 8-bit output code. |+| 7 | D5 | output | Digital data output bit 5 of the 8-bit output code. |+| 8 | D6 | output | Digital data output bit 6 of the 8-bit output code. |+| 9 | D7 | output | Digital data output bit 7 of the 8-bit output code. |+| 10 | D8 | output | Digital data output, D8 is the MSB of the 8-bit output code. |+| 11 | VDDD | power_in | Digital supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to DGND. |+| 12 | CLK | input | Clock input; high and low pulse durations must each be at least 25 ns, with VIH at least 4 V and VIL at most 1 V. |+| 13 | VDDD | power_in | Digital supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to DGND. |+| 14 | VDDA | power_in | Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND. |+| 15 | VDDA | power_in | Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND. |+| 16 | REFTS | passive | Top reference sense: shorted to REFT for the TLC5510 2-V internal divider configuration, and connected to VDDA for the TLC5510A 4-V configuration. |+| 17 | REFT | input | Top reference voltage; for the TLC5510A it must be at least VREFB + 2 V and at most 4 V. |+| 18 | VDDA | power_in | Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND. |+| 19 | ANALOG IN | input | Analog input whose range is VREFB to VREFT; the driving source resistance should be 10 Ω or less within the frequency range of interest. |+| 20 | AGND | power_in | Analog ground, to be tied to the analog ground plane. |+| 21 | AGND | power_in | Analog ground, to be tied to the analog ground plane. |+| 22 | REFBS | passive | Bottom reference sense: shorted to REFB for the TLC5510 2-V internal divider configuration, and connected to ground for the TLC5510A 4-V configuration. |+| 23 | REFB | input | Bottom reference voltage; for the TLC5510A it must be at least 0 V and at most VREFT - 4 V. |+| 24 | DGND | power_in | Digital ground; AGND and DGND are connected internally, so AGND-DGND must stay within -100 mV to 100 mV. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Data Acquisition |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `TLC5510IPWR`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `tlc5510ipwr-etched.step` / `tlc5510ipwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc5510ipwr.step` / `tlc5510ipwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlc5510) (22 pp, sha256 `342cbda59fa98fd6`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlc5510ipwr-datasheet.pdf)
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AGND and DGND are connected internally, so AGND-DGND must stay within -100 mV to 100 mV."+ },+ {+ "number": "3",+ "name": "D1",+ "type": "output",+ "description": "Digital data output, D1 is the LSB of the 8-bit output code."+ },+ {+ "number": "4",+ "name": "D2",+ "type": "output",+ "description": "Digital data output bit 2 of the 8-bit output code."+ },+ {+ "number": "5",+ "name": "D3",+ "type": "output",+ "description": "Digital data output bit 3 of the 8-bit output code."+ },+ {+ "number": "6",+ "name": "D4",+ "type": "output",+ "description": "Digital data output bit 4 of the 8-bit output code."+ },+ {+ "number": "7",+ "name": "D5",+ "type": "output",+ "description": "Digital data output bit 5 of the 8-bit output code."+ },+ {+ "number": "8",+ "name": "D6",+ "type": "output",+ "description": "Digital data output bit 6 of the 8-bit output code."+ },+ {+ "number": "9",+ "name": "D7",+ "type": "output",+ "description": "Digital data output bit 7 of the 8-bit output code."+ },+ {+ "number": "10",+ "name": "D8",+ "type": "output",+ "description": "Digital data output, D8 is the MSB of the 8-bit output code."+ },+ {+ "number": "11",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to DGND."+ },+ {+ "number": "12",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; high and low pulse durations must each be at least 25 ns, with VIH at least 4 V and VIL at most 1 V."+ },+ {+ "number": "13",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to DGND."+ },+ {+ "number": "14",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND."+ },+ {+ "number": "15",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND."+ },+ {+ "number": "16",+ "name": "REFTS",+ "type": "passive",+ "description": "Top reference sense: shorted to REFT for the TLC5510 2-V internal divider configuration, and connected to VDDA for the TLC5510A 4-V configuration."+ },+ {+ "number": "17",+ "name": "REFT",+ "type": "input",+ "description": "Top reference voltage; for the TLC5510A it must be at least VREFB + 2 V and at most 4 V."+ },+ {+ "number": "18",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog supply voltage, 4.75 V to 5.25 V (5 V nominal) referenced to AGND."+ },+ {+ "number": "19",+ "name": "ANALOG IN",+ "type": "input",+ "description": "Analog input whose range is VREFB to VREFT; the driving source resistance should be 10 Ω or less within the frequency range of interest."+ },+ {+ "number": "20",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground, to be tied to the analog ground plane."+ },+ {+ "number": "21",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground, to be tied to the analog ground plane."+ },+ {+ "number": "22",+ "name": "REFBS",+ "type": "passive",+ "description": "Bottom reference sense: shorted to REFB for the TLC5510 2-V internal divider configuration, and connected to ground for the TLC5510A 4-V configuration."+ },+ {+ "number": "23",+ "name": "REFB",+ "type": "input",+ "description": "Bottom reference voltage; for the TLC5510A it must be at least 0 V and at most VREFT - 4 V."+ },+ {+ "number": "24",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground; AGND and DGND are connected internally, so AGND-DGND must stay within -100 mV to 100 mV."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The top-view pin-name text on page 1 is extracted out of order, so pin numbers were assigned from th; The datasheet's Terminal Functions table gives no I/O direction for REFBS (22) and REFTS (16); types; Pins 3–10 are listed as 'O' in the datasheet; the output-enable text describes them as entering high"+ ],+ "pages_sent": 22,+ "cost_usd": 0.0967,+ "at": "2026-10-08T15:57:58"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlc5510",+ "pages": 22,+ "sha256": "342cbda59fa98fd6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlc5510ipwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlc5510ipwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c2366ecfa46e41890dae54bf3ae6a9afaac4d540805f9ce01e016df624bce93f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}