component
TLC4545IDR
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| tlc4545idr-etched.step | 7d ago |
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TLC4545IDR
Texas Instruments · Analog To Digital Converters (ADCs) · SOIC-8
TLC4545IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select: a high-to-low transition removes SDO from the high-impedance state within a maximum delay time, and SDO returns to high impedance on the rising edge of CS when no 17th SCLK cycle is presented. |
| 2 | REF | input | External voltage reference input, with a specified range of 4 V to VDD. |
| 3 | GND | power_in | Ground return for the internal circuitry; all voltage measurements are with respect to GND. |
| 4 | AIN(+) | input | Positive analog input for the TLC4545, with a recommended analog input voltage range of 0 V to VDD. |
| 5 | AIN(−) | input | Inverted analog input for the TLC4545, with a recommended analog input voltage range of −0.2 V to 0.2 V. |
| 6 | VDD | power_in | Positive supply voltage, 4.5 V to 5.5 V recommended (5 V nominal), with absolute maximum rating of −0.3 V to 6.5 V. |
| 7 | SCLK | input | Serial clock input from the host processor, operating from 100 kHz to 15 MHz at VDD = 2.7 V to 5.5 V. |
| 8 | SDO | output | 3-state serial data output carrying the A/D result MSB first; it is high impedance while CS is high and returns to high impedance after the 17th rising edge of SCLK. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VDD | VDD | 4.5 | 5 | 5.5 | V | 4 | |
| Frequency, SCLK | 100 | 15000 | kHz | VDD = 2.7 V to 5.5 V | 4 | ||
| Tolerable clock jitter, SCLK | 24 | ps | VDD = 2.7 V to 5.5 V | 4 | |||
| Aperture jitter | 100 | ps | VDD = 2.7 V to 5.5 V | 4 | |||
| External reference voltage input | VREF | 4 | V | 4 | |||
| VREF input impedance | 100 | MΩ | VDD = 5 V, CS = 1, SCLK = 0 | 4 | |||
| VREF input impedance | 20 | 25 | kΩ | VDD = 5 V, CS = 0, SCLK = 15 MHz | 4 | ||
| External reference input current | 0.02 | 1 | mA | VDD = VREF = 4.5 V, CS=0, SCLK = 15 MHz | 4 | ||
| Analog input voltage, AIN / AIN(+) | AIN | 0 | V | 4 | |||
| Analog input voltage, AIN(−) | AIN(−) | -0.2 | 0.2 | V | 4 | ||
| High level control input voltage | VIH | 2.1 | V | 4 | |||
| Low level control input voltage | VIL | 0.8 | V | 4 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | TLC4541/45I | 4 | |
| Supply voltage, GND to VDD | -0.3 | 6.5 | V | 4 | |||
| Analog input voltage range | -0.3 | V | 4 | ||||
| Digital input voltage range | -0.3 | V | 4 | ||||
| Operating virtual junction temperature range, TJ | TJ | -40 | 150 | °C | 4 | ||
| Operating free-air temperature range, TA (I) | TA | -40 | 85 | °C | 4 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature | 260 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 4 | |||
| High-level output voltage | VOH | 3.9 | V | VDD = 4.5 V, IOH = −0.2 mA | 5 | ||
| Low-level output voltage | VOL | 0.4 | V | VDD = 4.5 V, IOL = 0.8 mA | 5 | ||
| Off-state output current | IOZ | 1 | 2.5 | µA | VO = VDD, CS = VDD | 5 | |
| Off-state output current (high-impedance-state) | IOZ | -1 | -2.5 | µA | VO = 0, CS = VDD | 5 | |
| High-level input current | IIH | 0.005 | 2.5 | µA | VI = VDD | 5 | |
| Low-level input current | IIL | -0.005 | 2.5 | µA | VI = 0 | 5 | |
| Operating supply current | ICC | 3.5 | mA | CS at 0 V, VDD = 4.5 V to 5.5 V | 5 | ||
| Power-down supply current | ICC(PD) | 3 | 5 | µA | For all digital inputs, 0≤ VI ≤ 0.3 V or VI ≥ VDD − 0.3 V, SCLK=VDD, VDD = 4.5 V to 5.5 V | 5 | |
| Selected analog input channel leakage current | 1 | µA | Selected channel at VDD | 5 | |||
| A leakage current | -1 | µA | Selected channel at 0 V | 5 | |||
| Input capacitance, analog inputs | Ci | 11 | 14 | pF | Analog inputs | 5 | |
| Input capacitance, control inputs | Ci | 20 | 25 | pF | Control Inputs | 5 | |
| Input resistance | Zi | 500 | Ω | VDD = 5.5 V | 5 | ||
| Signal-to-noise ratio + distortion (SINAD) | SINAD | 84.5 | dB | fI = 15 kHz at 200 KSPS | 5 | ||
| Signal-to-noise ratio (SNR) | SNR | 85 | dB | fI = 15 kHz at 200 KSPS | 5 | ||
| Total harmonic distortion, TLC4545 | THD | -94 | -89 | dB | TLC4545 fI = 15 kHz at 200 KSPS | 5 | |
| Effective number of bits (ENOB) | ENOB | 13.7 | Bits | fI = 15 kHz at 200 KSPS | 5 | ||
| Spurious free dynamic range, TLC4545 | SFDR | -95 | -89 | dB | TLC4545 fI = 15 kHz at 200 KSPS | 5 | |
| Integral linearity error | INL | -2.5 | 2.5 | LSB | 5 | ||
| Differential linearity error | DNL | -1 | 2 | LSB | 5 | ||
| Offset error, TLC4545 | EO | -1 | 1 | mV | TLC4545 | 5 | |
| Gain error, TLC4545 | EG | -1.8 | 1.8 | mV | TLC4545 | 5 | |
| Cycle time, SCLK | tcyc(SCLK) | 66 | 10000 | ns | VDD = 4.5 V to 5.5 V | 6 | |
| Pulse width, SCLK low | tw1 | 27 | 5000 | ns | 6 | ||
| Pulse width, SCLK high | tw2 | 27 | 5000 | ns | 6 | ||
| Hold time, CS high after SCLK falling edge | th1 | 3 | ns | 6 | |||
| Setup time, CS falling edge before first SCLK falling edge | tsu1 | 15 | ns | 6 | |||
| Hold time, CS low after 16th SCLK falling edge | th2 | 5 | ns | 6 | |||
| Pulse width, CS high | tw3 | 0.5 | SCLKs | 6 | |||
| Delay time, CS falling edge to SDO MSB valid | td1 | 12 | 17 | ns | VDD = VREF = 4.5 V, 20 pF | 6 | |
| Delay time, SCLK rising edge to next SDO data bit valid | td2 | 15 | ns | VDD = VREF = 4.5 V, 20 pF | 6 | ||
| Delay time, 17th SCLK rising edge to SDO 3-stated | td3 | 20 | ns | VDD = VREF = 4.5 V, 20 pF | 6 | ||
| Hold time, CS low after 1st SCLK falling edge | th6 | 5 | ns | 6 | |||
| Setup time, CS rising edge before 9th (or last) SCLK falling edge | tsu6 | 5 | ns | 6 | |||
| Active CS/FS cycle time, SCLK falling edges to initialize ADC | tcyc(reset) | 1 | 8 | SCLKs | 6 | ||
| Conversion time (22 conversion clocks based on 7.5-MHz to 12-MHz OSC) | tconv | 1.83 | 2.94 | µs | 6 | ||
| Sample time, 20 SCLKs, SCLK up to 15 MHz | ts | 1.33 | 200 | µs | 6 |
CAD (KiCad official)
- Symbol:
TLC4545IDR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tlc4545idr-etched.step/tlc4545idr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc4545idr.step/tlc4545idr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
defa2df3d9eb76a7, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).