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TLC2932AIPWR
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLC2932AIPWR
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-14
TLC2932AIPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LOGIC VDD | power_in | Power supply for the internal logic, which should be separated from VCO VDD to reduce cross-coupling between supplies. |
| 2 | SELECT | input | VCO output frequency select: when SELECT is high the VCO output frequency is ×1/2, and when it is low the output frequency is ×1. |
| 3 | VCO OUT | output | VCO output, which is held low when VCO INHIBIT is high. |
| 4 | FIN-A | input | Input for the reference frequency f(REF IN), applied to FIN−A. |
| 5 | FIN-B | input | Input for the VCO external counter output frequency f(FIN−B), nominally provided from the external counter. |
| 6 | PFD OUT | output | PFD output, which is placed in the high-impedance state when PFD INHIBIT is high. |
| 7 | LOGIC GND | power_in | Ground reference for the internal logic. |
| 8 | TEST | passive | Connect to GND. |
| 9 | PFD INHIBIT | input | PFD inhibit control: when high, PFD OUT is placed in the high-impedance state and phase detection stops (power-down mode for the PFD). |
| 10 | VCO INHIBIT | input | VCO inhibit control: when high, the VCO stops oscillating, powers down, and VCO OUT is held low. |
| 11 | VCO GND | power_in | Ground reference for the VCO. |
| 12 | VCO IN | input | VCO control voltage input; nominally the external loop filter output connects here to control the VCO oscillation frequency. |
| 13 | RBIAS | input | Bias supply: an external resistor (RBIAS) connected between VCO VDD and this pin sets the bias for adjusting the oscillation frequency range (recommended bias resistor 2.2 kΩ to 5.1 kΩ). |
| 14 | VCO VDD | power_in | Power supply for the VCO, which should be separated from LOGIC VDD to reduce cross-coupling between supplies. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Clock/Timing |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
TLC2932AIPWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
tlc2932aipwr-etched.step/tlc2932aipwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc2932aipwr.step/tlc2932aipwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
f5e69e307df63a89, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).