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Ray tlc27l1idr: specified limits as data (metadata.characteristics, 49 rows from the datasheet) 2572aa8 14d ago

TLC27L1IDR

Texas Instruments · Operational Amplifier · SOIC-8

TLC27L1IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OFFSET N1	input	On legacy silicon this is the IN- offset adjustment pin (bias-select); on new silicon it is NC, a non-internally-connected pin.
2	IN-	input	Inverting input of the amplifier.
3	IN+	input	Noninverting input of the amplifier.
4	GND	power_in	Ground or negative (lowest) power supply.
5	OFFSET N2	input	On legacy silicon this is the IN+ offset adjustment pin (bias-select); on new silicon it is NC, a non-internally-connected pin.
6	OUT	output	Amplifier output.
7	VDD	power_in	Positive (highest) power supply; pin 7 is one of two VDD pins (pins 7 and 8) listed for this package.
8	VDD	power_in	Positive (highest) power supply; pin 8 is one of two VDD pins (pins 7 and 8) listed for this package.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Amplifiers/Comparators
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input offset voltage	VIO		1.1	10	mV	VDD = 5V; VO = 1.4V, VIC = 0V, RS = 50Ω, RI = 1MΩ; TA = 25°C	6
Input offset voltage	VIO			13	mV	VDD = 5V; VO = 1.4V, VIC = 0V, RS = 50Ω, RI = 1MΩ; TA = –40°C to +85°C	6
Input offset current	IIO		0.5	60	pA	VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 25°C	6
Input offset current	IIO		24	1000	pA	VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 85°C	6
Input offset current	IIO		26	1000	pA	VDD = 10V; VO = VDD/2, VIC = VDD/2; TA = 85°C	6
Input bias current	IIB		0.6	60	pA	VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 25°C	6
Input bias current	IIB		0.7	60	pA	VDD = 10V; VO = VDD/2, VIC = VDD/2; TA = 25°C	6
Input bias current	IIB		200	2000	pA	VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 85°C	6
Input bias current	IIB		220	2000	pA	VDD = 10V; VO = VDD/2, VIC = VDD/2; TA = 85°C	6
Common-mode input voltage range	VICR	-0.2		4	V	VDD = 5V; TA = 25°C	6
Common-mode input voltage range	VICR	-0.2		9	V	VDD = 10V; TA = 25°C	6
Common-mode input voltage range	VICR	-0.2		3.5	V	VDD = 5V; TA = –40°C to +85°C	6
Common-mode input voltage range	VICR	-0.2		8.5	V	VDD = 10V; TA = –40°C to +85°C	6
High-level output voltage	VOH	3	4.1		V	VDD = 5V; VID = 100mV, RL = 1MΩ; TA = 25°C	6
High-level output voltage	VOH	8	8.9		V	VDD = 10V; VID = 100mV, RL = 1MΩ; TA = 25°C	6
High-level output voltage	VOH	7.8	8.9		V	VDD = 10V; VID = 100mV, RL = 1MΩ; TA = –40°C	6
High-level output voltage	VOH	3	4.2		V	VDD = 5V; VID = 100mV, RL = 1MΩ; TA = 85°C	6
Low-level output voltage	VOL		1	50	mV	VDD = 5V; VID = –100mV, IOL = 0mA; TA = 25°C	6
Low-level output voltage	VOL		5	50	mV	VDD = 10V; VID = –100mV, IOL = 0mA; TA = 25°C	6
Large-signal differential voltage amplification	AVD	50	520		V/mV	VDD = 5V; RL = 1MΩ; VO = 0.25V to 2V; TA = 25°C	6
Large-signal differential voltage amplification	AVD	50	870		V/mV	VDD = 10V; RL = 1MΩ; VO = 1V to 6V; TA = 25°C	6
Large-signal differential voltage amplification	AVD	50	900		V/mV	VDD = 5V; RL = 1MΩ; VO = 0.25V to 2V; TA = –40°C	6
Large-signal differential voltage amplification	AVD	50	1550		V/mV	VDD = 10V; RL = 1MΩ; VO = 1V to 6V; TA = –40°C	6
Large-signal differential voltage amplification	AVD	50	330		V/mV	VDD = 5V; RL = 1MΩ; VO = 0.25V to 2V; TA = 85°C	6
Large-signal differential voltage amplification	AVD	50	585		V/mV	VDD = 10V; RL = 1MΩ; VO = 1V to 6V; TA = 85°C	6
Common-mode rejection ratio	CMRR	65	87		dB	VDD = 5V; VIC = VICRmin; TA = 25°C	6
Common-mode rejection ratio	CMRR	65	94		dB	VDD = 10V; VIC = VICRmin; TA = 25°C	6
Common-mode rejection ratio	CMRR	60	85		dB	VDD = 5V; VIC = VICRmin; TA = –40°C	6
Common-mode rejection ratio	CMRR	60	93		dB	VDD = 10V; VIC = VICRmin; TA = –40°C	6
Supply voltage rejection ratio (ΔVDD/ΔVIO)	kSVR	70	97		dB	VDD = 5V to 10V; VO = 1.4V; TA = 25°C	6
Supply voltage rejection ratio (ΔVDD/ΔVIO)	kSVR	60	97		dB	VDD = 5V to 10V; VO = 1.4V; TA = –40°C	6
Supply voltage rejection ratio (ΔVDD/ΔVIO)	kSVR	60	98		dB	VDD = 5V to 10V; VO = 1.4V; TA = 85°C	6
Offset adjustment pin input current (BIAS SELECT)	II(SEL)		65	95	nA	VI(SEL) = VDD, legacy silicon; TA = 25°C	6
Supply current	IDD		10	17	µA	VDD = 5V; VO = VDD/2, VIC = VDD/2, no load; TA = 25°C	6
Supply current	IDD		14	23	µA	VDD = 10V; VO = VDD/2, VIC = VDD/2, no load; TA = 25°C	6
Supply current	IDD		16	27	µA	VDD = 5V; VO = VDD/2, VIC = VDD/2, no load; TA = –40°C	6
Supply current	IDD		25	43	µA	VDD = 10V; VO = VDD/2, VIC = VDD/2, no load; TA = –40°C	6
Supply current	IDD		17	13	µA	VDD = 5V; VO = VDD/2, VIC = VDD/2, no load; TA = 85°C	6
Supply current	IDD		10	18	µA	VDD = 10V; VO = VDD/2, VIC = VDD/2, no load; TA = 85°C	6
Supply voltage	VDD	4		16	V	I suffix	3
Common-mode input voltage	VIC	-0.2		3.5	V	VDD = 5V	3
Common-mode input voltage	VIC	-0.2		8.5	V	VDD = 10V	3
Operating free-air temperature	TA	-40		85	°C	I suffix	3
Supply voltage	VDD			18	V		3
Input current	II	-5		5	mA		3
Output current	IO	-30		30	mA		3
Operating free-air temperature	TA	-40		85	°C	I suffix	3
Storage temperature	Tstg	-65		150	°C		3
Continuous total power dissipation (D package)				725	mW	D package; TA ≤ 25°C	3

CAD (KiCad official)

Symbol: TLC27L1IDR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tlc27l1idr-etched.step / tlc27l1idr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc27l1idr.step / tlc27l1idr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 85321b16d7768f5f, retrieved 2026-10-11, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TLC27L1IDR

**Texas Instruments** · Operational Amplifier · SOIC-8

TLC27L1IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OFFSET N1 | input | On legacy silicon this is the IN- offset adjustment pin (bias-select); on new silicon it is NC, a non-internally-connected pin. |
| 2 | IN- | input | Inverting input of the amplifier. |
| 3 | IN+ | input | Noninverting input of the amplifier. |
| 4 | GND | power_in | Ground or negative (lowest) power supply. |
| 5 | OFFSET N2 | input | On legacy silicon this is the IN+ offset adjustment pin (bias-select); on new silicon it is NC, a non-internally-connected pin. |
| 6 | OUT | output | Amplifier output. |
| 7 | VDD | power_in | Positive (highest) power supply; pin 7 is one of two VDD pins (pins 7 and 8) listed for this package. |
| 8 | VDD | power_in | Positive (highest) power supply; pin 8 is one of two VDD pins (pins 7 and 8) listed for this package. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input offset voltage | VIO |  | 1.1 | 10 | mV | VDD = 5V; VO = 1.4V, VIC = 0V, RS = 50Ω, RI = 1MΩ; TA = 25°C | 6 |
| Input offset voltage | VIO |  |  | 13 | mV | VDD = 5V; VO = 1.4V, VIC = 0V, RS = 50Ω, RI = 1MΩ; TA = –40°C to +85°C | 6 |
| Input offset current | IIO |  | 0.5 | 60 | pA | VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 25°C | 6 |
| Input offset current | IIO |  | 24 | 1000 | pA | VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 85°C | 6 |
| Input offset current | IIO |  | 26 | 1000 | pA | VDD = 10V; VO = VDD/2, VIC = VDD/2; TA = 85°C | 6 |
| Input bias current | IIB |  | 0.6 | 60 | pA | VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 25°C | 6 |
| Input bias current | IIB |  | 0.7 | 60 | pA | VDD = 10V; VO = VDD/2, VIC = VDD/2; TA = 25°C | 6 |
| Input bias current | IIB |  | 200 | 2000 | pA | VDD = 5V; VO = VDD/2, VIC = VDD/2; TA = 85°C | 6 |
| Input bias current | IIB |  | 220 | 2000 | pA | VDD = 10V; VO = VDD/2, VIC = VDD/2; TA = 85°C | 6 |
| Common-mode input voltage range | VICR | -0.2 |  | 4 | V | VDD = 5V; TA = 25°C | 6 |
| Common-mode input voltage range | VICR | -0.2 |  | 9 | V | VDD = 10V; TA = 25°C | 6 |
| Common-mode input voltage range | VICR | -0.2 |  | 3.5 | V | VDD = 5V; TA = –40°C to +85°C | 6 |
| Common-mode input voltage range | VICR | -0.2 |  | 8.5 | V | VDD = 10V; TA = –40°C to +85°C | 6 |
| High-level output voltage | VOH | 3 | 4.1 |  | V | VDD = 5V; VID = 100mV, RL = 1MΩ; TA = 25°C | 6 |
| High-level output voltage | VOH | 8 | 8.9 |  | V | VDD = 10V; VID = 100mV, RL = 1MΩ; TA = 25°C | 6 |
| High-level output voltage | VOH | 7.8 | 8.9 |  | V | VDD = 10V; VID = 100mV, RL = 1MΩ; TA = –40°C | 6 |
| High-level output voltage | VOH | 3 | 4.2 |  | V | VDD = 5V; VID = 100mV, RL = 1MΩ; TA = 85°C | 6 |
| Low-level output voltage | VOL |  | 1 | 50 | mV | VDD = 5V; VID = –100mV, IOL = 0mA; TA = 25°C | 6 |
| Low-level output voltage | VOL |  | 5 | 50 | mV | VDD = 10V; VID = –100mV, IOL = 0mA; TA = 25°C | 6 |
| Large-signal differential voltage amplification | AVD | 50 | 520 |  | V/mV | VDD = 5V; RL = 1MΩ; VO = 0.25V to 2V; TA = 25°C | 6 |
| Large-signal differential voltage amplification | AVD | 50 | 870 |  | V/mV | VDD = 10V; RL = 1MΩ; VO = 1V to 6V; TA = 25°C | 6 |
| Large-signal differential voltage amplification | AVD | 50 | 900 |  | V/mV | VDD = 5V; RL = 1MΩ; VO = 0.25V to 2V; TA = –40°C | 6 |
| Large-signal differential voltage amplification | AVD | 50 | 1550 |  | V/mV | VDD = 10V; RL = 1MΩ; VO = 1V to 6V; TA = –40°C | 6 |
| Large-signal differential voltage amplification | AVD | 50 | 330 |  | V/mV | VDD = 5V; RL = 1MΩ; VO = 0.25V to 2V; TA = 85°C | 6 |
| Large-signal differential voltage amplification | AVD | 50 | 585 |  | V/mV | VDD = 10V; RL = 1MΩ; VO = 1V to 6V; TA = 85°C | 6 |
| Common-mode rejection ratio | CMRR | 65 | 87 |  | dB | VDD = 5V; VIC = VICRmin; TA = 25°C | 6 |
| Common-mode rejection ratio | CMRR | 65 | 94 |  | dB | VDD = 10V; VIC = VICRmin; TA = 25°C | 6 |
| Common-mode rejection ratio | CMRR | 60 | 85 |  | dB | VDD = 5V; VIC = VICRmin; TA = –40°C | 6 |
| Common-mode rejection ratio | CMRR | 60 | 93 |  | dB | VDD = 10V; VIC = VICRmin; TA = –40°C | 6 |
| Supply voltage rejection ratio (ΔVDD/ΔVIO) | kSVR | 70 | 97 |  | dB | VDD = 5V to 10V; VO = 1.4V; TA = 25°C | 6 |
| Supply voltage rejection ratio (ΔVDD/ΔVIO) | kSVR | 60 | 97 |  | dB | VDD = 5V to 10V; VO = 1.4V; TA = –40°C | 6 |
| Supply voltage rejection ratio (ΔVDD/ΔVIO) | kSVR | 60 | 98 |  | dB | VDD = 5V to 10V; VO = 1.4V; TA = 85°C | 6 |
| Offset adjustment pin input current (BIAS SELECT) | II(SEL) |  | 65 | 95 | nA | VI(SEL) = VDD, legacy silicon; TA = 25°C | 6 |
| Supply current | IDD |  | 10 | 17 | µA | VDD = 5V; VO = VDD/2, VIC = VDD/2, no load; TA = 25°C | 6 |
| Supply current | IDD |  | 14 | 23 | µA | VDD = 10V; VO = VDD/2, VIC = VDD/2, no load; TA = 25°C | 6 |
| Supply current | IDD |  | 16 | 27 | µA | VDD = 5V; VO = VDD/2, VIC = VDD/2, no load; TA = –40°C | 6 |
| Supply current | IDD |  | 25 | 43 | µA | VDD = 10V; VO = VDD/2, VIC = VDD/2, no load; TA = –40°C | 6 |
| Supply current | IDD |  | 17 | 13 | µA | VDD = 5V; VO = VDD/2, VIC = VDD/2, no load; TA = 85°C | 6 |
| Supply current | IDD |  | 10 | 18 | µA | VDD = 10V; VO = VDD/2, VIC = VDD/2, no load; TA = 85°C | 6 |
| Supply voltage | VDD | 4 |  | 16 | V | I suffix | 3 |
| Common-mode input voltage | VIC | -0.2 |  | 3.5 | V | VDD = 5V | 3 |
| Common-mode input voltage | VIC | -0.2 |  | 8.5 | V | VDD = 10V | 3 |
| Operating free-air temperature | TA | -40 |  | 85 | °C | I suffix | 3 |
| Supply voltage | VDD |  |  | 18 | V |  | 3 |
| Input current | II | -5 |  | 5 | mA |  | 3 |
| Output current | IO | -30 |  | 30 | mA |  | 3 |
| Operating free-air temperature | TA | -40 |  | 85 | °C | I suffix | 3 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| Continuous total power dissipation (D package) |  |  |  | 725 | mW | D package; TA ≤ 25°C | 3 |

## CAD (KiCad official)

- Symbol: `TLC27L1IDR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tlc27l1idr-etched.step` / `tlc27l1idr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc27l1idr.step` / `tlc27l1idr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlc27l1.pdf) (35 pp, sha256 `85321b16d7768f5f`, retrieved 2026-10-11, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlc27l1idr-datasheet.pdf)