component

TLC2652CN

Public Made by Adom

by adom

Texas Instruments Pre-ordered Chips, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icstlc2652cnfactory-2.0.0extractor-text

Verified TLC2652CN

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TLC2652CN · PDIP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 41-page datasheet
  • ✓distributor: lcsc C1347050, digikey 2156-TLC2652CN-ND, mouser 595-TLC2652CN
  • ✓family: DIP-14_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-aqapm81w/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tlc2652cn.kicad_sym✓ tlc2652cn.kicad_mod✓ tlc2652cn.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers tlc2652cn: viewers · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
tlc2652cn-etched.glb Publish 0.1.0 · Ray 10d ago
tlc2652cn-etched.step tlc2652cn: factory component page (tier=mfr) · Ray 10d ago
tlc2652cn-hero.glb tlc2652cn: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
tlc2652cn-hero.overlay.json Publish 0.1.0 · Ray 10d ago
tlc2652cn.glb Publish 0.1.0 · Ray 10d ago
tlc2652cn.kicad_mod Publish 0.1.0 · Ray 10d ago
tlc2652cn.kicad_sym Publish 0.1.0 · Ray 10d ago
tlc2652cn.lbr Publish 0.1.0 · Ray 10d ago
tlc2652cn.step Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 14 pins · Ray 10d ago

TLC2652CN

Texas Instruments · Pre-ordered Chips · PDIP-14

TLC2652CN from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CXB passive Connection for external nulling capacitor CXB (0.1 µF to 1 µF), returned to VDD− or C RETURN.
2 CXA passive Connection for external nulling capacitor CXA (0.1 µF to 1 µF), returned to VDD− or C RETURN.
3 NC unconnected No internal connection.
4 IN− input Inverting input of the op amp; input voltage limited to ±8 V and differential input to ±16 V.
5 IN+ input Noninverting input of the op amp; common-mode range includes the negative rail, VDD− to VDD+ −1.9 V.
6 NC unconnected No internal connection.
7 VDD− power_in Negative supply, absolute maximum −8 V; also the reference for the clock input range and a return for CXA/CXB.
8 C RETURN passive Return connection for the external capacitors CXA and CXB, alternative to VDD−.
9 CLAMP passive Output clamp, connected to the inverting input to reduce overload recovery time; activates when output is about 1 V from either rail.
10 OUT output Amplifier output, up to ±50 mA output current with short-circuit to either supply allowed within dissipation limits.
11 VDD+ power_in Positive supply, absolute maximum 8 V; operating supply is ±1.9 V to ±8 V.
12 CLK OUT output Internal clock output of the chopper control circuitry.
13 CLK IN input External clock input, range VDD− to VDD− +5 V with trip point 2.5 V above the negative rail, used when INT/EXT is tied to VDD−.
14 INT/EXT input Clock select: leave unconnected for the internal 450-Hz clock, or connect to VDD− to use the external clock on CLK IN.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Interface ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD+ VDD+ 8 V see Note 1 (voltages relative to midpoint of VDD+ and VDD−) 4
Supply voltage VDD− VDD− -8 V see Note 1 4
Differential input voltage VID -16 16 V see Note 2 (IN+ with respect to IN−) 4
Input voltage (any input) VI -8 8 V see Note 1 4
Input current (each input) II -5 5 mA each input 4
Output current IO -50 50 mA 4
Current into CLK IN and INT/EXT -5 5 mA 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature (D, N, or P package) 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 4
Supply voltage VDD± VDD± 1.9 8 V C suffix; magnitude of ±VDD (printed ±1.9 min, ±8 max) 4
Operating free-air temperature TA 0 70 °C C suffix 4
Power rating at TA = 70°C (N package) 1008 mW Dissipation rating table, N package, TA = 70°C 4
Power rating at TA ≤ 25°C (N package) 1575 mV Dissipation rating table, N package, TA ≤ 25°C; unit as printed 4
VIO Input offset voltage VIO 0.6 3 µV 25°C; VDD± = ±5 V 5
VIO Input offset voltage (full range) VIO 4.35 µV Full range (0 to 70°C); VDD± = ±5 V 5
Temperature coefficient of input offset voltage αVIO 0.003 0.03 µV/°C Full range 5
Input offset voltage long-term drift 0.003 0.06 µV/mo VIC = 0, RS = 50 Ω, 25°C 5
Input offset current IIO 2 60 pA 25°C 5
Input offset current (full range) IIO 100 pA Full range 5
Input bias current IIB 4 60 pA 25°C 5
Input bias current (full range) IIB 100 pA Full range 5
Common-mode input voltage range VICR -5 3.1 V RS = 50 Ω, Full range 5
Maximum positive peak output voltage swing VOM+ 4.7 4.8 V RL = 10 kΩ, 25°C; output clamp not connected 5
Maximum positive peak output voltage swing (full range) VOM+ 4.7 V RL = 10 kΩ, Full range 5
Maximum negative peak output voltage swing VOM− -4.7 -4.9 V RL = 10 kΩ, 25°C; output clamp not connected 5
Maximum negative peak output voltage swing (full range) VOM− -4.7 V RL = 10 kΩ, Full range 5
Large-signal differential voltage amplification AVD 120 150 dB VO = ±4 V, RL = 10 kΩ, 25°C 5
Large-signal differential voltage amplification (full range) AVD 120 dB VO = ±4 V, RL = 10 kΩ, Full range 5
Clamp on-state current 25 µA RL = 100 kΩ, 25°C 5
Clamp on-state current (full range) 25 µA RL = 100 kΩ, Full range 5
Clamp off-state current 100 pA VO = −4 V to 4 V, 25°C 5
Clamp off-state current (full range) 100 pA VO = −4 V to 4 V, Full range 5
Common-mode rejection ratio CMRR 120 140 dB VO = 0, VIC = VICRmin, 25°C 5
Common-mode rejection ratio (full range) CMRR 120 dB VO = 0, VIC = VICRmin, RS = 50 Ω, Full range 5
Supply-voltage rejection ratio kSVR 110 135 dB VDD± = ±1.9 V to ±8 V, 25°C 5
Supply-voltage rejection ratio (full range) kSVR 110 dB VDD± = ±1.9 V to ±8 V, Full range 5
Supply current IDD 1.5 2.4 mA 25°C 5
Supply current (full range) IDD 2.5 mA Full range 5
Positive slew rate at unity gain SR+ 2 2.8 V/µs VO = ±2.3 V, RL = 10 kΩ, 25°C 6
Positive slew rate at unity gain (full range) SR+ 1.5 V/µs VO = ±2.3 V, RL = 10 kΩ, Full range 6
Negative slew rate at unity gain SR− 2.3 3.1 V/µs RL = 10 kΩ, CL = 100 pF, 25°C 6
Negative slew rate at unity gain (full range) SR− 1.8 V/µs RL = 10 kΩ, CL = 100 pF, Full range 6
Equivalent input noise voltage Vn 94 nV/√Hz f = 10 Hz, 25°C 6
Equivalent input noise voltage Vn 23 nV/√Hz f = 1 kHz, 25°C 6
Peak-to-peak equivalent input noise voltage VN(PP) 0.8 µV f = 0 to 1 Hz, 25°C 6
Peak-to-peak equivalent input noise voltage VN(PP) 2.8 µV f = 0 to 10 Hz, 25°C 6
Equivalent input noise current In 0.004 fA/√Hz f = 10 kHz, 25°C 6
Gain-bandwidth product 1.9 MHz RL = 10 kΩ, CL = 100 pF, 25°C 6
Phase margin at unity gain φm 48 ° RL = 10 kΩ, CL = 100 pF, 25°C 6
Internal chopping frequency fch 450 Hz 25°C 5

CAD (KiCad official)

  • Symbol: TLC2652CN
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: tlc2652cn-etched.step / tlc2652cn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc2652cn.step / tlc2652cn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 896e351d66293f04, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF