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TLC2543CDWR

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Texas Instruments Analog To Digital Converters (ADCs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLC2543CDWR

Texas Instruments · Analog To Digital Converters (ADCs) · SOIC-20-300mil

TLC2543CDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN0 input Multiplexed analog input channel 0; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
2 AIN1 input Multiplexed analog input channel 1; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
3 AIN2 input Multiplexed analog input channel 2; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
4 AIN3 input Multiplexed analog input channel 3; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
5 AIN4 input Multiplexed analog input channel 4; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
6 AIN5 input Multiplexed analog input channel 5; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
7 AIN6 input Multiplexed analog input channel 6; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
8 AIN7 input Multiplexed analog input channel 7; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
9 AIN8 input Multiplexed analog input channel 8; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
10 GND power_in Ground return terminal for the internal circuitry; all voltage measurements are referenced to GND.
11 AIN9 input Multiplexed analog input channel 9; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
12 AIN10 input Multiplexed analog input channel 10; the driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF.
13 REF- input Negative reference voltage, nominally ground; the lower reference value is applied here and the input range is set by the difference from REF+.
14 REF+ input Positive reference voltage, nominally VCC; the maximum input voltage range is the difference between this terminal and REF-.
15 CS input Chip select; a high-to-low transition resets the internal counters and enables DATA OUT, DATA INPUT and I/O CLOCK, and a low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time.
16 DATA OUT tri_state 3-state serial output for the A/D conversion result, in high impedance when CS is high and active when CS is low, shifting out the MSB/LSB-first result on each falling edge of I/O CLOCK.
17 DATA INPUT input Serial-data input where a 4-bit MSB-first address selects the next analog input or self-test voltage, shifted in on the first four rising edges of I/O CLOCK.
18 I/O CLOCK input Input/output clock that shifts in the address and control bits, starts the sample period after the fourth falling edge, and transfers conversion control on the last falling edge; it operates at 0 to 4.1 MHz with 120 ns minimum high and low pulse widths.
19 EOC output End-of-conversion output that goes low after the last falling edge of I/O CLOCK and returns high when the conversion is complete and the data is ready for transfer.
20 VCC power_in Positive supply voltage, specified at 4.5 V minimum, 5 V nominal and 5.5 V maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category ADC/DAC/Data Conversion
Pins 20

CAD (KiCad official)

  • Symbol: TLC2543CDWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: tlc2543cdwr-etched.step / tlc2543cdwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc2543cdwr.step / tlc2543cdwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 4f0ece16b966081b, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF