component
TLC2274ACDR
Public Made by Adomby adom
UMW Operational Amplifier, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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tlc2274acdr: specified limits as data (metadata.characteristics, 32 rows from the datasheet)
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TLC2274ACDR
UMW · Operational Amplifier · SOP-14
TLC2274ACDR from UMW, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OUT | output | Output of op-amp channel 1. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
| 2 | 1IN- | input | Inverting input of op-amp channel 1. High-impedance CMOS input, typical input bias current 1 pA. |
| 3 | 1IN+ | input | Non-inverting input of op-amp channel 1. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 4 | VDD+ | power_in | Positive (highest) supply pin. Absolute maximum 8 V with respect to the VDD+/VDD- midpoint (16 V max across supplies). |
| 5 | 2IN+ | input | Non-inverting input of op-amp channel 2. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 6 | 2IN- | input | Inverting input of op-amp channel 2. High-impedance CMOS input, typical input bias current 1 pA. |
| 7 | 2OUT | output | Output of op-amp channel 2. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
| 8 | 3OUT | output | Output of op-amp channel 3. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
| 9 | 3IN- | input | Inverting input of op-amp channel 3. High-impedance CMOS input, typical input bias current 1 pA. |
| 10 | 3IN+ | input | Non-inverting input of op-amp channel 3. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 11 | VDD- | power_in | Negative (lowest) supply pin. Tie to GND for single-supply operation or to a negative rail (down to -8 V max) for split-supply operation. |
| 12 | 4IN+ | input | Non-inverting input of op-amp channel 4. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 13 | 4IN- | input | Inverting input of op-amp channel 4. High-impedance CMOS input, typical input bias current 1 pA. |
| 14 | 4OUT | output | Output of op-amp channel 4. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-14 |
| Category | Op-amp/Cmp |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
TLC2274ACDRTLC2274ACDRD
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD+ | VDD+ | 8 | V | 4 | |||
| Supply voltage VDD- | VDD- | -8 | V | 4 | |||
| Differential input voltage | VID | -16 | 16 | V | 4 | ||
| Input current (any input) | II | -5 | 5 | mA | 4 | ||
| Output current | IO | -50 | 50 | mA | 4 | ||
| Total current into VDD+ | 50 | mA | 4 | ||||
| Total current out of VDD- | 50 | mA | 4 | ||||
| Operating free-air temperature range | TA | 0 | 70 | °C | C level parts | 4 | |
| Storage temperature | TSTG | -65 | 150 | °C | 4 | ||
| Lead temperature 1,6 mm from case | 260 | °C | for 10 seconds | 4 | |||
| Input offset voltage | VIO | 950 | µV | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=25°C; VDD=5V | 11 | ||
| Input offset voltage | VIO | 1500 | µV | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; Full Range(1) | 11 | ||
| Input offset current | IIO | 60 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=25°C | 11 | ||
| Input offset current | IIO | 100 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=0°C to 80°C (C level part) | 11 | ||
| Input bias current | IIB | 60 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=25°C | 11 | ||
| Input bias current | IIB | 100 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=0°C to 80°C (C level part) | 11 | ||
| High-level output voltage | VOH | 4.99 | V | IOH=-20µA; TA=25°C; VDD=5V | 11 | ||
| High-level output voltage | VOH | 4.93 | V | IOH=-200µA; TA=25°C; VDD=5V | 11 | ||
| High-level output voltage | VOH | 4.65 | V | IOH=-1mA; TA=25°C; VDD=5V | 11 | ||
| Low-level output voltage | VOL | 0.01 | V | IOL=50µA; TA=25°C; VDD=5V | 12 | ||
| Low-level output voltage | VOL | 0.09 | V | IOL=500µA; TA=25°C; VDD=5V | 12 | ||
| Low-level output voltage | VOL | 0.9 | V | IOL=5mA; TA=25°C; VDD=5V | 12 | ||
| Common-mode rejection ratio | CMRR | 70 | dB | VIC=0V to 2.7V, VO=2.5V, RS=50Ω; TA=25°C; VDD=5V | 12 | ||
| Supply-voltage rejection ratio (ΔVDD/ΔVIO) | kSVR | 80 | dB | VDD=4.4V to 16V, VIC=VDD/2, no load; TA=25°C; VDD=5V | 12 | ||
| Supply current | IDD | 2.3 | mA | VO=0V, no load; VDD±=±5V; TA=25°C | 15 | ||
| Common-mode rejection ratio | CMRR | 75 | dB | VIC=-5V to 2.7V, VO=0V, RS=50Ω; TA=25°C; VDD=±5V | 15 | ||
| Supply-voltage rejection ratio (ΔVDD/ΔVIO) | kSVR | 80 | dB | VDD+=2.2V to ±8V, VIC=0V, no load; TA=25°C; VDD=±5V | 15 | ||
| Junction-to-ambient thermal resistance (D SOP 14-PIN) | RθJA | 83.8 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance (D SOP 14-PIN) | RθJC(top) | 43.2 | °C/W | 5 | |||
| Junction-to-board thermal resistance (D SOP 14-PIN) | RθJB | 38.4 | °C/W | 5 | |||
| Junction-to-top characterization parameter (D SOP 14-PIN) | ΨJT | 9.4 | °C/W | 5 | |||
| Junction-to-board characterization parameter (D SOP 14-PIN) | ΨJB | 38.1 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TLC2274ACDR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
tlc2274acdr-etched.step/tlc2274acdr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc2274acdr.step/tlc2274acdr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tlc2274acdr.step |
195 KB | You want the bare part, or you mark your own boards. |
tlc2274acdr-etched.step |
2.2 MB | You want the part with TLC2274ACDR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 568 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (30 pp, sha256
ead5615846e4c74e, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TLC2274ACDR
**UMW** · Operational Amplifier · SOP-14
TLC2274ACDR from UMW, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OUT | output | Output of op-amp channel 1. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
| 2 | 1IN- | input | Inverting input of op-amp channel 1. High-impedance CMOS input, typical input bias current 1 pA. |
| 3 | 1IN+ | input | Non-inverting input of op-amp channel 1. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 4 | VDD+ | power_in | Positive (highest) supply pin. Absolute maximum 8 V with respect to the VDD+/VDD- midpoint (16 V max across supplies). |
| 5 | 2IN+ | input | Non-inverting input of op-amp channel 2. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 6 | 2IN- | input | Inverting input of op-amp channel 2. High-impedance CMOS input, typical input bias current 1 pA. |
| 7 | 2OUT | output | Output of op-amp channel 2. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
| 8 | 3OUT | output | Output of op-amp channel 3. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
| 9 | 3IN- | input | Inverting input of op-amp channel 3. High-impedance CMOS input, typical input bias current 1 pA. |
| 10 | 3IN+ | input | Non-inverting input of op-amp channel 3. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 11 | VDD- | power_in | Negative (lowest) supply pin. Tie to GND for single-supply operation or to a negative rail (down to -8 V max) for split-supply operation. |
| 12 | 4IN+ | input | Non-inverting input of op-amp channel 4. High-impedance CMOS input with common-mode range including the negative supply rail. |
| 13 | 4IN- | input | Inverting input of op-amp channel 4. High-impedance CMOS input, typical input bias current 1 pA. |
| 14 | 4OUT | output | Output of op-amp channel 4. Rail-to-rail output, capable of sourcing/sinking up to ±50 mA (absolute max). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-14 |
| Category | Op-amp/Cmp |
| Pins | 14 |
## Ordering variants
Same part, different packaging or reel option.
- `TLC2274ACDR`
- `TLC2274ACDRD`
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD+ | VDD+ | | | 8 | V | | 4 |
| Supply voltage VDD- | VDD- | -8 | | | V | | 4 |
| Differential input voltage | VID | -16 | | 16 | V | | 4 |
| Input current (any input) | II | -5 | | 5 | mA | | 4 |
| Output current | IO | -50 | | 50 | mA | | 4 |
| Total current into VDD+ | | | | 50 | mA | | 4 |
| Total current out of VDD- | | | | 50 | mA | | 4 |
| Operating free-air temperature range | TA | 0 | | 70 | °C | C level parts | 4 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 4 |
| Lead temperature 1,6 mm from case | | | | 260 | °C | for 10 seconds | 4 |
| Input offset voltage | VIO | | | 950 | µV | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=25°C; VDD=5V | 11 |
| Input offset voltage | VIO | | | 1500 | µV | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; Full Range(1) | 11 |
| Input offset current | IIO | | | 60 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=25°C | 11 |
| Input offset current | IIO | | | 100 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=0°C to 80°C (C level part) | 11 |
| Input bias current | IIB | | | 60 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=25°C | 11 |
| Input bias current | IIB | | | 100 | pA | VIC=0V, VDD±=±2.5V, VO=0V, RS=50Ω; TA=0°C to 80°C (C level part) | 11 |
| High-level output voltage | VOH | 4.99 | | | V | IOH=-20µA; TA=25°C; VDD=5V | 11 |
| High-level output voltage | VOH | 4.93 | | | V | IOH=-200µA; TA=25°C; VDD=5V | 11 |
| High-level output voltage | VOH | 4.65 | | | V | IOH=-1mA; TA=25°C; VDD=5V | 11 |
| Low-level output voltage | VOL | | | 0.01 | V | IOL=50µA; TA=25°C; VDD=5V | 12 |
| Low-level output voltage | VOL | | | 0.09 | V | IOL=500µA; TA=25°C; VDD=5V | 12 |
| Low-level output voltage | VOL | | | 0.9 | V | IOL=5mA; TA=25°C; VDD=5V | 12 |
| Common-mode rejection ratio | CMRR | 70 | | | dB | VIC=0V to 2.7V, VO=2.5V, RS=50Ω; TA=25°C; VDD=5V | 12 |
| Supply-voltage rejection ratio (ΔVDD/ΔVIO) | kSVR | 80 | | | dB | VDD=4.4V to 16V, VIC=VDD/2, no load; TA=25°C; VDD=5V | 12 |
| Supply current | IDD | | | 2.3 | mA | VO=0V, no load; VDD±=±5V; TA=25°C | 15 |
| Common-mode rejection ratio | CMRR | 75 | | | dB | VIC=-5V to 2.7V, VO=0V, RS=50Ω; TA=25°C; VDD=±5V | 15 |
| Supply-voltage rejection ratio (ΔVDD/ΔVIO) | kSVR | 80 | | | dB | VDD+=2.2V to ±8V, VIC=0V, no load; TA=25°C; VDD=±5V | 15 |
| Junction-to-ambient thermal resistance (D SOP 14-PIN) | RθJA | | 83.8 | | °C/W | | 5 |
| Junction-to-case (top) thermal resistance (D SOP 14-PIN) | RθJC(top) | | 43.2 | | °C/W | | 5 |
| Junction-to-board thermal resistance (D SOP 14-PIN) | RθJB | | 38.4 | | °C/W | | 5 |
| Junction-to-top characterization parameter (D SOP 14-PIN) | ΨJT | | 9.4 | | °C/W | | 5 |
| Junction-to-board characterization parameter (D SOP 14-PIN) | ΨJB | | 38.1 | | °C/W | | 5 |
## CAD (KiCad official)
- Symbol: `TLC2274ACDR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `tlc2274acdr-etched.step` / `tlc2274acdr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc2274acdr.step` / `tlc2274acdr.glb` are the bare package body.
## 3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
| [`tlc2274acdr.step`](tlc2274acdr.step) | 195 KB | You want the bare part, or you mark your own boards. |
| [`tlc2274acdr-etched.step`](tlc2274acdr-etched.step) | 2.2 MB | You want the part with `TLC2274ACDR` already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 568 faces against 237 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](docs/tlc2274acdr-datasheet.pdf) (30 pp, sha256 `ead5615846e4c74e`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tlc2274acdr-datasheet.pdf)