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TLC2272AMD

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Texas Instruments Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icstlc2272amdfactory-2.0.0extractor-text

Verified TLC2272AMD

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TLC2272AMD · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 56-page datasheet
  • ✓distributor: lcsc C1346967, digikey 296-7113-5-ND, mouser 595-TLC2272AMD
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_kuk0gwj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.46)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tlc2272amd.kicad_sym✓ tlc2272amd.kicad_mod✓ tlc2272amd.step
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Ray Publish 0.1.0 8c21beb 10d ago

TLC2272AMD

Texas Instruments · Pre-ordered Chips · SOIC-8

TLC2272AMD from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Output of channel 1; the output swing includes both supply rails.
2 1IN- input Inverting input of channel 1; the input voltage must stay between VDD- and VDD+ − 1.5 V (recommended operating condition).
3 1IN+ input Non-inverting input of channel 1; the common-mode input range includes the negative rail, and the input voltage must stay between VDD- and VDD+ − 1.5 V.
4 VDD-/GND power_in Negative (lowest) supply; the recommended split supply range is VDD± = ±2.2 V to ±8 V.
5 2IN+ input Non-inverting input of channel 2; the common-mode input range includes the negative rail, and the input voltage must stay between VDD- and VDD+ − 1.5 V.
6 2IN- input Inverting input of channel 2; the input voltage must stay between VDD- and VDD+ − 1.5 V (recommended operating condition).
7 2OUT output Output of channel 2; the output swing includes both supply rails.
8 VDD+ power_in Positive (highest) supply; the recommended split supply range is VDD± = ±2.2 V to ±8 V, and the absolute maximum VDD+ is 8 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage, TLC2272A, TA = 25°C VIO 300 950 µV VDD = 5 V; VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω 6
Input offset voltage, TLC2272A, Full Range VIO 1500 µV VDD = 5 V; VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω; Full Range 6
Input offset current, all level parts IIO 0.5 60 pA VDD = 5 V; VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω; TA = 25°C 6
Input offset current, M level part IIO 800 pA VDD = 5 V; VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω; TA = −55°C to 125°C 6
Input bias current, all level parts IIB 1 60 pA VDD = 5 V; VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω; TA = 25°C 6
Input bias current, M level part IIB 800 pA VDD = 5 V; VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω; TA = −55°C to 125°C 6
Common-mode input voltage range VICR -0.3 2.5 4 V VDD = 5 V; RS = 50 Ω; /VIO/ ≤ 5 mV; TA = 25°C 6
Common-mode input voltage range, Full Range VICR 0 2.5 3.5 V VDD = 5 V; RS = 50 Ω; /VIO/ ≤ 5 mV; Full Range 6
High-level output voltage VOH 4.85 4.93 V VDD = 5 V; IOH = −200 µA; TA = 25°C 7
High-level output voltage, Full Range VOH 4.85 V VDD = 5 V; IOH = −200 µA; Full Range 7
High-level output voltage VOH 4.25 4.65 V VDD = 5 V; IOH = −1 mA; TA = 25°C 7
High-level output voltage, Full Range VOH 4.25 V VDD = 5 V; IOH = −1 mA; Full Range 7
Low-level output voltage VOL 0.09 0.15 V VDD = 5 V; VIC = 2.5 V, IOL = 500 µA; TA = 25°C 7
Low-level output voltage, Full Range VOL 0.15 V VDD = 5 V; VIC = 2.5 V, IOL = 500 µA; Full Range 7
Low-level output voltage VOL 0.9 1.5 V VDD = 5 V; VIC = 2.5 V, IOL = 5 mA; TA = 25°C 7
Low-level output voltage, Full Range VOL 1.5 V VDD = 5 V; VIC = 2.5 V, IOL = 5 mA; Full Range 7
Large-signal differential voltage amplification, M level part AVD 10 35 V/mV VDD = 5 V; VIC = 2.5 V, VO = 1 V to 4 V; RL = 10 kΩ; TA = 25°C 7
Large-signal differential voltage amplification, M level part AVD 10 V/mV VDD = 5 V; VIC = 2.5 V, VO = 1 V to 4 V; RL = 10 kΩ; TA = −55°C to 125°C 7
Common-mode rejection ratio CMRR 70 75 dB VDD = 5 V; VIC = 0 V to 2.7 V, VO = 2.5 V, RS = 50 Ω; TA = 25°C 7
Common-mode rejection ratio, Full Range CMRR 70 dB VDD = 5 V; VIC = 0 V to 2.7 V, VO = 2.5 V, RS = 50 Ω; Full Range 7
Supply-voltage rejection ratio kSVR 80 95 dB VDD = 5 V; VDD = 4.4 V to 16 V, VIC = VDD / 2, no load; TA = 25°C 7
Supply-voltage rejection ratio, Full Range kSVR 80 dB VDD = 5 V; VDD = 4.4 V to 16 V, VIC = VDD / 2, no load; Full Range 7
Supply current IDD 2.2 3 mA VDD = 5 V; VO = 2.5 V, no load; TA = 25°C 7
Supply current, Full Range IDD 3 mA VDD = 5 V; VO = 2.5 V, no load; Full Range 7
Slew rate at unity gain SR 2.3 3.6 V/µs VDD = 5 V; VO = 0.5 V to 2.5 V, RL = 10 kΩ, CL = 100 pF; TA = 25°C 7
Slew rate at unity gain, Full Range SR 1.7 V/µs VDD = 5 V; VO = 0.5 V to 2.5 V, RL = 10 kΩ, CL = 100 pF; Full Range 7
Input offset voltage, TLC2272A, TA = 25°C VIO 300 950 µV VDD± = ±5 V; VIC = 0 V, VO = 0 V, RS = 50 Ω; TA = 25°C 8
Input offset voltage, TLC2272A, Full Range VIO 1500 µV VDD± = ±5 V; VIC = 0 V, VO = 0 V, RS = 50 Ω; Full Range 8
Input offset current, all level parts IIO 0.5 60 pA VDD± = ±5 V; VIC = 0 V, VO = 0 V, RS = 50 Ω; TA = 25°C 8
Input offset current, M level part IIO 800 pA VDD± = ±5 V; VIC = 0 V, VO = 0 V, RS = 50 Ω; TA = −55°C to 125°C 8
Input bias current, all level parts IIB 1 60 pA VDD± = ±5 V; VIC = 0 V, VO = 0 V, RS = 50 Ω; TA = 25°C 8
Input bias current, M level part IIB 800 pA VDD± = ±5 V; VIC = 0 V, VO = 0 V, RS = 50 Ω; TA = −55°C to 125°C 8
Common-mode input voltage range VICR -5.3 0 4 V VDD± = ±5 V; RS = 50 Ω; /VIO/ ≤ 5 mV; TA = 25°C 8
Common-mode input voltage range, Full Range VICR -5 0 3.5 V VDD± = ±5 V; RS = 50 Ω; /VIO/ ≤ 5 mV; Full Range 8
Maximum positive peak output voltage VOM+ 4.85 4.93 V VDD± = ±5 V; IO = −200 µA; TA = 25°C 8
Maximum positive peak output voltage, Full Range VOM+ 4.85 V VDD± = ±5 V; IO = −200 µA; Full Range 8
Maximum positive peak output voltage VOM+ 4.25 4.65 V VDD± = ±5 V; IO = −1 mA; TA = 25°C 8
Maximum positive peak output voltage, Full Range VOM+ 4.25 V VDD± = ±5 V; IO = −1 mA; Full Range 8
Large-signal differential voltage amplification, M level part AVD 20 50 V/mV VDD± = ±5 V; VO = ±4 V; RL = 10 kΩ; TA = 25°C 8
Large-signal differential voltage amplification, M level part AVD 20 V/mV VDD± = ±5 V; VO = ±4 V; RL = 10 kΩ; TA = −55°C to 125°C 8
Common-mode rejection ratio CMRR 75 80 dB VDD± = ±5 V; VIC = −5 V to 2.7 V, VO = 0 V, RS = 50 Ω; TA = 25°C 8
Common-mode rejection ratio, Full Range CMRR 75 dB VDD± = ±5 V; VIC = −5 V to 2.7 V, VO = 0 V, RS = 50 Ω; Full Range 8
Supply-voltage rejection ratio kSVR 80 95 dB VDD± = ±5 V; VDD+ = 2.2 V to ±8 V, VIC = 0 V, no load; TA = 25°C 8
Supply-voltage rejection ratio, Full Range kSVR 80 dB VDD± = ±5 V; VDD+ = 2.2 V to ±8 V, VIC = 0 V, no load; Full Range 8
Supply current IDD 2.4 3 mA VDD± = ±5 V; VO = 0 V, no load; TA = 25°C 8
Supply current, Full Range IDD 3 mA VDD± = ±5 V; VO = 0 V, no load; Full Range 8
Slew rate at unity gain SR 2.3 3.6 V/µs VDD± = ±5 V; VO = ±2.3 V, RL = 10 kΩ, CL = 100 pF; TA = 25°C 9
Slew rate at unity gain, Full Range SR 1.7 V/µs VDD± = ±5 V; VO = ±2.3 V, RL = 10 kΩ, CL = 100 pF; Full Range 9
Supply voltage (recommended, M level parts) VDD± 2.2 8 V M level parts 6
Operating free-air temperature (recommended, M level parts) TA -55 125 °C M level parts 6
Supply voltage, VDD+ VDD+ 8 V All voltages referenced to the midpoint between VDD+ and VDD− 5
Supply voltage, VDD− VDD- -8 V All voltages referenced to the midpoint between VDD+ and VDD− 5
Differential input voltage VID -16 16 V Differential voltages are at IN+ with respect to IN− 5
Input current (any input) II -5 5 mA 5
Output current IO -50 50 mA 5
Total current into VDD+ -50 50 mA 5
Total current out of VDD− -50 50 mA 5
Operating free-air temperature range, TA TA -55 125 °C M level parts 5
Storage temperature, Tstg Tstg -65 150 °C 5
Junction-to-ambient thermal resistance, D (SOIC) 8-pin RθJA 115.6 °C/W TA = −55°C to 125°C 6

CAD (KiCad official)

  • Symbol: TLC2272AMD
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tlc2272amd-etched.step / tlc2272amd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc2272amd.step / tlc2272amd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 0065915d5b2f28de, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF