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TLC0820AIN
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLC0820AIN
Texas Instruments · Analog To Digital Converters (ADC) · PDIP-20
TLC0820AIN from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ANLG IN | input | Analog input; the recommended analog input voltage range is -0.1 V to VCC + 0.1 V. |
| 2 | D0 | tri_state | Digital 3-state output data, bit 1 (LSB). |
| 3 | D1 | tri_state | Digital 3-state output data, bit 2. |
| 4 | D2 | tri_state | Digital 3-state output data, bit 3. |
| 5 | D3 | tri_state | Digital 3-state output data, bit 4. |
| 6 | WR/RDY | bidirectional | Write ready: in write-read mode with CS low, conversion starts on the falling edge of WR; in read mode RDY is an open-drain output that goes low after the falling edge of CS and goes high-impedance when the result is strobed into the output latch. |
| 7 | MODE | input | Mode select: low selects read mode and high selects write-read mode; MODE is internally tied to GND through a 50-µA current source acting as a pulldown. |
| 8 | RD | input | Read: in write-read mode with CS low, enables the 3-state data outputs when taken low, and in read mode with CS low, starts the conversion on its falling edge. |
| 9 | INT | output | Interrupt output: in write-read mode it goes low when the internal delay td(int) (typically 800 ns after the rising edge of WR) completes and the data is in the output latch, and it is reset by the rising edge of RD or CS. |
| 10 | GND | power_in | Ground; all voltages are referenced to network GND. |
| 11 | REF- | input | Negative reference voltage, placed on the bottom of the resistor ladder; recommended range is GND to Vref+. |
| 12 | REF+ | input | Positive reference voltage, placed on the top of the resistor ladder; recommended range is Vref- to VCC. |
| 13 | CS | input | Chip select: CS must be low for RD or WR to be recognized by the ADC. |
| 14 | D4 | tri_state | Digital 3-state output data, bit 5. |
| 15 | D5 | tri_state | Digital 3-state output data, bit 6. |
| 16 | D6 | tri_state | Digital 3-state output data, bit 7. |
| 17 | D7 | tri_state | Digital 3-state output data, bit 8 (MSB). |
| 18 | OFLW | output | Overflow: normally high, it goes low at the end of conversion if the analog input is higher than Vref+, and it can be used to cascade two or more devices for 9- or 10-bit resolution. |
| 19 | NC | unconnected | No internal connection. |
| 20 | VCC | power_in | Power supply voltage; recommended supply range is 4.5 V to 8 V with 5 V nominal. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-20 |
| Category | Data Acquisition |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
TLC0820AIN - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: PDIP-20 (KiCad packages3D, STEP)
- 3D model files:
tlc0820ain-etched.step/tlc0820ain-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc0820ain.step/tlc0820ain.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
917edde6a8b5098a, retrieved 2026-10-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).