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TLC072CDR

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Texas Instruments Operational Amplifier, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLC072CDR

Texas Instruments · Operational Amplifier · SOIC-8

TLC072CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Channel 1 amplifier output, capable of 57 mA source at VDD-1.5 V and 55 mA sink at 0.5 V.
2 1IN− input Channel 1 inverting input.
3 1IN+ input Channel 1 non-inverting input, common-mode range 0.5 V to VDD−0.8 V.
4 GND power_in Negative supply/ground; all voltages except differentials are referenced to it.
5 2IN+ input Channel 2 non-inverting input, common-mode range 0.5 V to VDD−0.8 V.
6 2IN− input Channel 2 inverting input.
7 2OUT output Channel 2 amplifier output, capable of 57 mA source at VDD-1.5 V and 55 mA sink at 0.5 V.
8 VDD power_in Positive supply, 4.5 V to 16 V single supply (17 V absolute maximum).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Amplifiers
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 390 1900 µV VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω, 25°C 5
Input offset voltage, full range VIO 3000 µV VDD = 5 V, Full range 5
Input offset current IIO 0.7 50 pA VDD = 5 V, 25°C 5
Input offset current, full range IIO 100 pA VDD = 5 V, C suffix, Full range 5
Input bias current IIB 1.5 50 pA VDD = 5 V, 25°C 5
Input bias current, full range IIB 100 pA VDD = 5 V, C suffix, Full range 5
Common-mode input voltage VICR 0.5 4.2 V VDD = 5 V, RS = 50 Ω, 25°C 5
High-level output voltage VOH 4.1 4.3 V VDD = 5 V, IOH = −1 mA, 25°C 5
High-level output voltage VOH 3.7 4 V VDD = 5 V, IOH = −20 mA, 25°C 5
High-level output voltage VOH 3.4 3.8 V VDD = 5 V, IOH = −35 mA, 25°C 5
High-level output voltage VOH 3.2 3.6 V VDD = 5 V, IOH = −50 mA, 25°C 5
Low-level output voltage VOL 0.18 0.25 V VDD = 5 V, IOL = 1 mA, 25°C 5
Low-level output voltage VOL 0.35 0.39 V VDD = 5 V, IOL = 20 mA, 25°C 5
Low-level output voltage VOL 0.43 0.55 V VDD = 5 V, IOL = 35 mA, 25°C 5
Low-level output voltage VOL 0.48 0.63 V VDD = 5 V, IOL = 50 mA, 25°C 5
Large-signal differential voltage amplification AVD 100 120 dB VDD = 5 V, VO(PP) = 3 V, RL = 10 kΩ, 25°C 6
Large-signal differential voltage amplification, full range AVD 100 dB VDD = 5 V, VO(PP) = 3 V, RL = 10 kΩ, Full range 6
Common-mode rejection ratio CMRR 80 95 dB VDD = 5 V, VIC = 1 to 3 V, RS = 50 Ω, 25°C 6
Supply voltage rejection ratio kSVR 80 100 dB VDD = 4.5 V to 16 V, VIC = VDD/2, No load, 25°C 6
Supply current (per channel) IDD 1.9 2.5 mA VDD = 5 V, VO = 2.5 V, No load, 25°C 6
Supply current (per channel), full range IDD 3.5 mA VDD = 5 V, VO = 2.5 V, No load, Full range 6
Positive slew rate at unity gain SR+ 10 16 V/µs VDD = 5 V, VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ, 25°C 7
Negative slew rate at unity gain SR− 12.5 19 V/µs VDD = 5 V, VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ, 25°C 7
Input offset voltage VIO 390 1900 µV VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω, 25°C 8
Input offset voltage, full range VIO 3000 µV VDD = 12 V, Full range 8
Common-mode input voltage VICR 0.5 11.2 V VDD = 12 V, RS = 50 Ω, 25°C 8
High-level output voltage VOH 11.1 11.2 V VDD = 12 V, IOH = −1 mA, 25°C 8
High-level output voltage VOH 10.8 10.9 V VDD = 12 V, IOH = −20 mA, 25°C 8
High-level output voltage VOH 10.6 10.7 V VDD = 12 V, IOH = −35 mA, 25°C 8
High-level output voltage VOH 10.4 10.5 V VDD = 12 V, IOH = −50 mA, 25°C 8
Low-level output voltage VOL 0.17 0.25 V VDD = 12 V, IOL = 1 mA, 25°C 8
Low-level output voltage VOL 0.35 0.45 V VDD = 12 V, IOL = 20 mA, 25°C 8
Low-level output voltage VOL 0.4 0.52 V VDD = 12 V, IOL = 35 mA, 25°C 8
Low-level output voltage VOL 0.45 0.6 V VDD = 12 V, IOL = 50 mA, 25°C 8
Large-signal differential voltage amplification AVD 120 140 dB VDD = 12 V, VO(PP) = 8 V, RL = 10 kΩ, 25°C 9
Common-mode rejection ratio CMRR 80 100 dB VDD = 12 V, VIC = 1 to 10 V, RS = 50 Ω, 25°C 9
Supply current (per channel) IDD 2.1 2.9 mA VDD = 12 V, VO = 7.5 V, No load, 25°C 9
Supply current (per channel), full range IDD 3.5 mA VDD = 12 V, VO = 7.5 V, No load, Full range 9
Positive slew rate at unity gain SR+ 10 16 V/µs VDD = 12 V, VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ, 25°C 10
Negative slew rate at unity gain SR− 12.5 19 V/µs VDD = 12 V, VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ, 25°C 10
Temperature coefficient of input offset voltage αVIO 1.2 µV/°C VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω 5
Supply voltage, single supply VDD 4.5 16 V Single supply 4
Supply voltage, split supply VDD -2.25 -8 V Split supply, printed ±2.25 to ±8 4
Common-mode input voltage VICR 0.5 V Min +0.5 V; max VDD−0.8 V 4
Operating free-air temperature, C suffix TA 0 70 °C C-suffix 4
Supply voltage VDD 17 V With respect to GND 4
Maximum junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 4
Operating free-air temperature range, C suffix TA 0 70 °C C suffix 4
Junction-to-ambient thermal resistance, D (8) θJA 176 °C/W D (8) package; power rating 710 mW at TA ≤ 25°C 4
Junction-to-case thermal resistance, D (8) θJC 38.3 °C/W D (8) package 4

CAD (KiCad official)

  • Symbol: TLC072CDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tlc072cdr-etched.step / tlc072cdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc072cdr.step / tlc072cdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (63 pp, sha256 0129518e2bec43cd, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF