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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	tl494idrg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
viewers	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
package.json	Publish 0.2.0 · Ray	1mo ago
pads.json	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
page.json	Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray	11d ago
README.md	tl494idrg: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	15d ago
tl494idrg-etched.fit.json	tl494idrg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
tl494idrg-etched.glb	tl494idrg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
tl494idrg-etched.step	tl494idrg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
tl494idrg.glb	Publish 0.1.0 · Ray	1mo ago
tl494idrg.kicad_mod	Publish 0.1.0 · Ray	1mo ago
tl494idrg.kicad_sym	Publish 0.1.0 · Ray	1mo ago
tl494idrg.lbr	rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 16 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray	1mo ago
tl494idrg.step	Publish 0.1.0 · Ray	1mo ago

TL494IDRG

HANSCHIP semiconductor · AC-DC Controllers and Regulators · SOP-16

TL494IDRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1IN+	input	Non-inverting input of error amplifier 1. Common-mode input range is -0.3 V to VCC-2 V.
2	1IN-	input	Inverting input of error amplifier 1. Common-mode input range is -0.3 V to VCC-2 V.
3	FEEDBACK	bidirectional	Feedback / PWM comparator input. The wired-OR outputs of both error amplifiers appear here and are compared with the oscillator ramp. Input threshold ~4.5 V (zero duty cycle); can source ~2 mA and sink ~0.3 mA.
4	DTC	input	Dead-time control input. A voltage on this pin sets the minimum dead-time (maximum duty cycle). 0 V gives maximum duty cycle; ~3.3 V forces zero duty cycle. Input bias current ~10 uA over 0-5.25 V.
5	CT	passive	Oscillator timing capacitor connection. External capacitor to GND sets the oscillator frequency together with RT (typ. C=0.01 uF, R=12 k gives ~10 kHz).
6	RT	passive	Oscillator timing resistor connection. External resistor to GND sets the oscillator charging current and, together with CT, the oscillator frequency.
7	GND	power_in	Device ground return.
8	C1	output	Collector of output transistor 1 (uncommitted). Rated to 500 mA source/sink (200 mA recommended), VCE(max) 40 V, VCE(sat) ~1.3 V @ 200 mA. Used for push-pull (with C2/pin 11) or single-ended output.
9	E1	output	Emitter of output transistor 1 (uncommitted). Tie to GND for common-emitter (open-collector) operation or use as an emitter-follower output.
10	E2	output	Emitter of output transistor 2 (uncommitted). Tie to GND for common-emitter (open-collector) operation or use as an emitter-follower output.
11	C2	output	Collector of output transistor 2 (uncommitted). Rated to 500 mA source/sink (200 mA recommended), VCE(max) 40 V. Used for push-pull (with C1/pin 8) or single-ended output.
12	VCC	power_in	Main supply voltage. Recommended 7-40 V, absolute maximum 41 V. Standby current ~10 mA at 15 V, ~15 mA at 40 V.
13	OUTPUT CTRL	input	Output-mode control. Tie to GND for parallel single-ended operation of both output transistors (in phase); tie to VREF (pin 14) for push-pull operation via the pulse-steering flip-flop. Input current ~3.5 mA.
14	VREF	power_out	5.0 V internal reference output (4.75-5.25 V @ IO=1 mA, VCC=15 V). Short-circuit current limited to ~50 mA; drift <1 % over -40 to +85 degC.
15	2IN-	input	Inverting input of error amplifier 2. Common-mode input range is -0.3 V to VCC-2 V.
16	2IN+	input	Non-inverting input of error amplifier 2. Common-mode input range is -0.3 V to VCC-2 V. Typically tied to GND (or VREF) when only one error amp is used.

Key specifications

Parameter	Value
Manufacturer	HANSCHIP semiconductor
Package	SOP-16
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

TL494CDRG
TL494CDRG4
TL494IDRG
TL494IDRG4
TL494CPG
TL494IPG
TL494CPWRG
TL494IPWRG

CAD (KiCad official)

Symbol: TL494IDRG
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)
3D model files: tl494idrg-etched.step / tl494idrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl494idrg.step / tl494idrg.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tl494idrg.step`	217 KB	You want the bare part, or you mark your own boards.
`tl494idrg-etched.step`	2.1 MB	You want the part with `TL494IDRG` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 543 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HANSCHIP semiconductor datasheet (9 pp, sha256 bd4b68a7f8cb0624, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF