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TL432 0.5%

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UMW Voltage Reference, SOT-23-3. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpmictl432 0.5%
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TL432 0.5%

UMW · Voltage Reference · SOT-23-3

TL432 0.5% from UMW, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R input Reference input. Internal error amplifier compares this pin against the 1.25 V band-gap reference; when V(R) exceeds Vref the device sinks current from cathode to anode. Reference input current Iref is typically 1.5 uA (max 4 uA); maximum reference input current rating is 6 mA.
2 K passive Cathode. Programmable shunt terminal; sinks current to the anode to regulate V(KA) to the set point defined by the external divider (VKA = Vref (1 + R1/R2) + Iref x R1). Maximum cathode voltage 18 V, continuous cathode current 100 mA, dynamic impedance typ 0.15 ohm.
3 A passive Anode. Common return terminal, typically tied to circuit ground/negative supply of the shunt reference.

Key specifications

Parameter Value
Manufacturer UMW
Package SOT-23-3
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • TL432 0.5%UMW TL432 0.5%

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reference voltage Vref 1.243 1.25 1.256 V VKA=VREF, IKA=10mA 3
Cathode Voltage VKA 18 V 2
Cathode Current Range (Continuous) IKA 100 mA 2
Reference Input Current Range Iref 6 mA 2
Power Dissipation PD 350 mW 2
Thermal Resistance from Junction to Ambient RθJA 350 °C/W 2
Operating Junction Temperature TJ 125 °C 2
Operating Ambient Temperature Range Topr -40 105 °C 2
Storage temperature Range TSTG -40 150 °C 2

CAD (KiCad official)

  • Symbol: TL432 0.5%
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3 (KiCad packages3D, STEP)
  • 3D model files: tl432-0-5-etched.step / tl432-0-5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl432-0-5.step / tl432-0-5.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tl432-0-5.step 59 KB You want the bare part, or you mark your own boards.
tl432-0-5-etched.step 1.7 MB You want the part with TL432 0.5% already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 416 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (7 pp, sha256 3e3595dac7d171a8, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF