Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TL3844BDR

Texas Instruments · AC-DC Controllers And Regulators · SOIC-14

TL3844BDR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier compensation pin. Provides access to the error amplifier output for loop compensation networks between COMP and VFB. Typical high-level output ≥5 V, low-level ≤1.1 V; source ≈0.5 mA, sink ≈2 mA.
2 VFB input Error amplifier inverting input (voltage feedback). Regulated to the internal reference divided down to ~2.5 V. Input bias current ≈ -0.3 µA typ.
3 ISENSE input Current-sense comparator input. Trips the PWM latch at ~1.0 V typ (0.9-1.1 V), providing cycle-by-cycle peak current limiting. Input range 0 V to 5.5 V; propagation delay to output ≈150 ns typ.
4 RT/CT bidirectional Oscillator RC input. External timing resistor to VREF and timing capacitor to GND set the oscillator frequency (up to 500 kHz recommended). Trimmed internal discharge current ≈8.3 mA typ; output frequency is one-half the oscillator frequency on the TL3844B (internal toggle flip-flop).
5 GND power_in Device power supply ground (analog/signal and PWM return). All device voltages are referenced to this terminal. On the 8-pin package, output ground and signal ground share this pin.
6 OUTPUT output Totem-pole PWM output for driving an N-channel power MOSFET gate. Delivers high peak current with rise/fall times ≈25 ns typ (150 ns max) into 1 nF; average output current up to 200 mA. VOH ≈13.5 V @ IOH = -20 mA; VOL ≈0.1 V @ IOL = 20 mA. Held low in UVLO (VOL ≤1.2 V while sinking 10 mA).
7 VCC power_in Device positive supply. UVLO start threshold ≈16 V (14.5-17.5 V), stop threshold ≈10 V (8.5-11.5 V). Absolute maximum 30 V (low-impedance source) or self-limiting for ICC < 30 mA; start-up current <0.5 mA, operating current ≈11 mA typ (17 mA max).
8 VREF power_out Internally trimmed 5 V reference output (5.0 V ±0.1 V at TJ = 25 °C, IO = 1 mA). Sources up to 20 mA (short-circuit current -100 mA typ) for external bias including the RT/CT timing resistor.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Power Management (PMIC)
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • TL3844BDRD
  • TL3844BDR
  • TL3844BDRIDR
  • TL3844BDRIDGSR
  • TL3844BDRP
  • TL3844BDRD (14)

CAD (KiCad official)

  • Symbol: TL3844BDR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: tl3844bdr-etched.step / tl3844bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl3844bdr.step / tl3844bdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 42e42dc7a6e780d9, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF