component

TL3116IDR

Public Made by Adom

by adom

Texas Instruments Comparators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentoperational amplifier-comparatortl3116idrfactory-2.0.0extractor-text

Verified TL3116IDR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TL3116IDR · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C2870041, digikey 296-TL3116IDRTR-ND, mouser 595-TL3116IDR
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-e03badgj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tl3116idr.kicad_sym✓ tl3116idr.kicad_mod✓ tl3116idr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers tl3116idr: viewers · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
tl3116idr-etched.glb Publish 0.1.0 · Ray 4d ago
tl3116idr-etched.step tl3116idr: factory component page (tier=mfr) · Ray 4d ago
tl3116idr-hero.glb tl3116idr: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
tl3116idr-hero.overlay.json Publish 0.1.0 · Ray 4d ago
tl3116idr.glb Publish 0.1.0 · Ray 4d ago
tl3116idr.kicad_mod Publish 0.1.0 · Ray 4d ago
tl3116idr.kicad_sym Publish 0.1.0 · Ray 4d ago
tl3116idr.lbr Publish 0.1.0 · Ray 4d ago
tl3116idr.step Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 4d ago

TL3116IDR

Texas Instruments · Comparators · SOIC-8

TL3116IDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC+ power_in Positive supply pin; the part operates from a single 5-V supply or from split ±5-V supplies, with absolute maximum supply voltage of ±7 V.
2 IN+ input Non-inverting comparator input; the input common-mode range extends to the negative rail (VICR −5 V to 2.5 V at VDD = ±5 V).
3 IN− input Inverting comparator input; differential input voltage is specified as IN+ with respect to IN−, with a 7 V maximum.
4 VCC− power_in Negative supply pin for split ±5-V operation; the negative supply is specified from −7 V to −2 V in the supply-rejection test conditions.
5 LATCH ENABLE input Latch enable input; its high-level input voltage is at least 2 V and its low-level input voltage is at most 0.8 V.
6 GND power_in Ground reference pin; all voltage values except differential voltages are referenced to network ground.
7 Q OUT output Complementary comparator output (inverse of the Q OUT pin 8); output sink current is limited to ±20 mA absolute maximum.
8 Q OUT output Comparator output; the device has complementary outputs that can be latched using the LATCH ENABLE terminal, with output current limited to ±20 mA absolute maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input offset voltage VIO 0.5 3 mV TA = 25°C 4
Input offset voltage VIO 3.5 mV TA = full range 4
Input offset current IIO 0.1 0.2 µA TA = 25°C 4
Input offset current IIO 0.35 µA TA = full range 4
Input bias current IIB 0.7 1.1 µA TA = 25°C 4
Input bias current IIB 1.5 µA TA = full range 4
Common-mode input voltage range VICR -5 2.5 V VDD = ±5 V 4
Common-mode input voltage range VICR 0 2.5 V VDD = 5 V 4
Common-mode rejection ratio CMRR 75 100 dB −5 ≤ VIC ≤ 2.5 V 4
Supply-voltage rejection ratio (positive supply) kSVR 60 80 dB Positive supply: 4.6 V ≤ +VDD ≤ 5.4 V, TA = 25°C 4
Supply-voltage rejection ratio (negative supply) kSVR 80 100 dB Negative supply: −7 V ≤ −VDD ≤ −2 V, TA = 25°C 4
Low-level output voltage VOL 400 600 mV I(sink) = 4 mA, V+ ≤ 4.6 V, TA = 25°C 4
Low-level output voltage VOL 750 mV I(sink) = 10 mA, V+ ≤ 4.6 V, TA = 25°C 4
High-level output voltage VOH 3.6 3.9 V V+ ≤ 4.6 V, IO = 1 mA, TA = 25°C 4
High-level output voltage VOH 3.4 3.8 V V+ ≤ 4.6 V, IO = 10 mA, TA = 25°C 4
Positive supply current ICC 12.7 15 mA TA = full range 4
Negative supply current ICC -2.6 -3 mA TA = full range 4
Low-level input voltage (LATCH ENABLE) VIL 0.8 V LATCH ENABLE 4
High-level input voltage (LATCH ENABLE) VIH 2 V LATCH ENABLE 4
Low-level input current (LATCH ENABLE) IIL 0 1 µA VLE = 0 4
Low-level input current (LATCH ENABLE) IIL 24 45 µA VLE = 2 V 4
Temperature coefficient of input offset voltage αVIO -2.8 µV/°C 4
Propagation delay time tpd1 9.9 12 ns ∆VI = 100 mV, TA = 25°C 5
Propagation delay time tpd1 9.9 15 ns ∆VI = 100 mV, VOD = 5 mV, TA = full range 5
Propagation delay time tpd1 8.2 10.3 ns ∆VI = 100 mV, VOD = 20 mV, TA = 25°C 5
Propagation delay time tpd1 8.2 13.7 ns ∆VI = 100 mV, VOD = 20 mV, TA = full range 5
Pulse skew (/tpd+ − tpd−/) tsk(p) 0.5 ns ∆VI = 100 mV, TA = 25°C, VOD = 5 mV 5
Setup time, LATCH ENABLE tsu 3.4 ns 5
Supply voltage VDD -7 7 V 3
Differential input voltage VID 7 V 3
Input voltage range VI 7 V 3
Input voltage (LATCH ENABLE) VI 7 V LATCH ENABLE 3
Output current IO -20 20 mA 3
Operating free-air temperature range TA -40 85 °C 3
Storage temperature range Tstg -65 150 °C 3
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 3
Power rating, D package 725 mW TA ≤ 25°C 3
Derating factor above TA = 25°C, D package 5.8 mW/°C above TA = 25°C 3
Power rating at TA = 70°C, D package 464 mW TA = 70°C 3
Power rating, PW package 525 mW TA ≤ 25°C 3
Derating factor above TA = 25°C, PW package 4.2 mW/°C above TA = 25°C 3
Power rating at TA = 70°C, PW package 336 mW TA = 70°C 3

CAD (KiCad official)

  • Symbol: TL3116IDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tl3116idr-etched.step / tl3116idr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl3116idr.step / tl3116idr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 86b4a0323deeafdd, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF