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TL16C750EPFBR

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Texas Instruments UART, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TL16C750EPFBR

Texas Instruments · UART · TQFP-48(7x7)

TL16C750EPFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 D5 bidirectional Data bus bit 5 of the 8-bit 3-state bidirectional bus used to transfer information to or from the controlling CPU.
3 D6 bidirectional Data bus bit 6 of the 8-bit 3-state bidirectional bus used to transfer information to or from the controlling CPU.
4 D7 bidirectional Data bus bit 7 of the 8-bit 3-state bidirectional bus used to transfer information to or from the controlling CPU.
5 NC unconnected No internal connection.
6 NC unconnected No internal connection.
7 RX input Receive data input that should be held high when no data is being received in normal mode, and is disabled during local loopback mode.
8 TX output Transmit serial data output; during local loopback mode the TX pin is disabled and TX data is connected internally to the UART RX input.
9 NC unconnected No internal connection.
10 MODE input Interface mode select that must be tied to VCC or GND; at VCC IOR is used for communication, and at GND only IOW is sampled when CS toggles low and IOR must be connected to VCC.
11 CS input Chip select; when low this input enables the ACE, and when high the ACE remains inactive.
12 NC unconnected No internal connection.
13 NC unconnected No internal connection.
14 XTAL1 input Crystal or external clock input; a crystal between XTAL1 and XTAL2 forms the internal oscillator, or an external clock can be applied for custom data rates.
15 XTAL2 output Output of the crystal oscillator or buffered clock output.
16 IOW input Active-low write strobe; a valid low transfers the data bus (D0-D7) into the internal register selected by A0-A2.
17 NC unconnected No internal connection.
18 VSS power_in Ground power reference.
19 IOR input Active-low read input; while the ACE is selected, the CPU reads status information or data from ACE registers.
20 NC unconnected No internal connection.
21 NC unconnected No internal connection.
22 NC unconnected No internal connection.
23 TXRDY output Transmit ready, active low; goes low when a trigger level number of spaces is available and goes high when the TX buffer is full.
24 NC unconnected No internal connection.
25 NC unconnected No internal connection.
26 A2 input Address bit 2 for selecting internal registers, per the register address map.
27 A1 input Address bit 1 for selecting internal registers, per the register address map.
28 A0 input Address bit 0 for selecting internal registers, per the register address map.
29 RXRDY output Receive ready, active low; goes low when the trigger level is reached or a timeout interrupt occurs, and goes high when the RX FIFO is empty or has an error.
30 INT output Interrupt output that becomes active for a receiver error, received data available or timed out (FIFO mode), an empty transmitter holding register, or an enabled modem status interrupt, and is cleared when serviced or by master reset.
31 OP output User-defined output controlled by MCR bit 3: logic 0 with INT active when MCR-3 is 1, and logic 1 with INT 3-state when MCR-3 is 0.
32 RTS output Request to send, active when the ACE is ready to receive data; set inactive (high) by master reset, loop mode, clearing MCR bit 1, or by receiver threshold logic in auto-RTS mode.
33 DTR output Data terminal ready, active low to inform a modem that the ACE is ready; can also control an external RS-485 driver or transceiver.
34 NC unconnected No internal connection.
35 RESET input Reset input that resets the internal registers and all outputs, and disables the UART transmitter output and receiver input during reset.
36 NC unconnected No internal connection.
37 NC unconnected No internal connection.
38 CTS input Clear to send modem status signal, also used in auto-CTS mode to control the transmitter.
39 DSR input Data set ready modem status signal; a change generates an interrupt when the modem status interrupt is enabled.
40 CD input Carrier detect, active low; a low indicates that a carrier has been detected by the modem.
41 RI input Ring indicator modem status signal; a low-to-high transition is flagged in the modem status register and generates an interrupt when enabled.
42 VCC power_in Power supply input; the datasheet specifies VCC from 1.62 V to 5.5 V across its operating conditions.
43 D0 bidirectional Data bus bit 0, the least significant bit and first bit in a transmit or receive serial data stream.
44 D1 bidirectional Data bus bit 1 of the 8-bit 3-state bidirectional bus used to transfer information to or from the controlling CPU.
45 D2 bidirectional Data bus bit 2 of the 8-bit 3-state bidirectional bus used to transfer information to or from the controlling CPU.
46 D3 bidirectional Data bus bit 3 of the 8-bit 3-state bidirectional bus used to transfer information to or from the controlling CPU.
47 D4 bidirectional Data bus bit 4 of the 8-bit 3-state bidirectional bus used to transfer information to or from the controlling CPU.
48 NC unconnected No internal connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: TL16C750EPFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: tl16c750epfbr-etched.step / tl16c750epfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl16c750epfbr.step / tl16c750epfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 015cd6a2020c34dd, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF