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TL16C550DPTR
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Texas Instruments UART, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+84@@ -0,0 +1,84 @@+# TL16C550DPTR++**Texas Instruments** · UART · LQFP-48(7x7)++TL16C550DPTR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | No internal connection; leave this pin unconnected. |+| 2 | D5 | bidirectional | Data bus line D5 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 3 | D6 | bidirectional | Data bus line D6 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 4 | D7 | bidirectional | Data bus line D7 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 5 | RCLK | input | Receiver clock is the 16x baud rate clock for the receiver section of the ACE. |+| 6 | NC | unconnected | No internal connection; leave this pin unconnected. |+| 7 | SIN | input | Serial data input receives serial data from the connected communications device. |+| 8 | SOUT | output | Serial data output sends composite serial data to the connected communication device and is set to marking (high) by master reset. |+| 9 | CS0 | input | Chip select 0: with CS1 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive. |+| 10 | CS1 | input | Chip select 1: with CS0 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive. |+| 11 | CS2 | input | Chip select 2: with CS0 and CS1 high and CS2 low, this input selects the ACE; when inactive the ACE remains inactive. |+| 12 | BAUDOUT | output | Baud out provides a 16x transmitter clock whose rate is set by the reference oscillator divided by the baud generator divisor; it may be tied to RCLK for receiver clocking. |+| 13 | NC | unconnected | No internal connection; leave this pin unconnected. |+| 14 | XIN | bidirectional | External clock input connects the ACE to the main timing reference (clock or crystal) together with XOUT. |+| 15 | XOUT | bidirectional | External clock output connects the ACE to the main timing reference (crystal) together with XIN. |+| 16 | WR1 | input | Write input 1: when active (low) with WR2 tied inactive (high) and the ACE selected, the CPU may write control words or data. |+| 17 | WR2 | input | Write input 2: when active (high) with WR1 tied inactive (low) and the ACE selected, the CPU may write control words or data. |+| 18 | VSS | power_in | Supply common (ground) for the device. |+| 19 | RD1 | input | Read input 1: when active (low) with the ACE selected, the CPU may read status or data from the selected ACE register; RD2 must be tied to its inactive level. |+| 20 | RD2 | input | Read input 2: when active (high) with the ACE selected, the CPU may read status or data from the selected ACE register; RD1 must be tied to its inactive level. |+| 21 | NC | unconnected | No internal connection; leave this pin unconnected. |+| 22 | DDIS | output | Driver disable is active (high) when the CPU is not reading data and can disable an external transceiver. |+| 23 | TXRDY | output | Transmitter ready provides transmitter DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode). |+| 24 | ADS | input | Address strobe: when active (low), A0-A2 and CS0-CS2 drive the select logic directly; when high, they are held at their levels at the low-to-high ADS transition. |+| 25 | NC | unconnected | No internal connection; leave this pin unconnected. |+| 26 | A2 | input | Register select bit 2 selects the ACE register for read or write operations (see Table 1). |+| 27 | A1 | input | Register select bit 1 selects the ACE register for read or write operations (see Table 1). |+| 28 | A0 | input | Register select bit 0 selects the ACE register for read or write operations (see Table 1). |+| 29 | RXRDY | output | Receiver ready provides receiver DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode) and goes active low when data is available. |+| 30 | INTRPT | output | Interrupt output is active (high) to inform the CPU of a receiver error, received data, an empty transmitter holding register or a modem status interrupt. |+| 31 | OUT2 | output | User-designated output 2 is forced low when MCR bit 3 is set and high when cleared, and is high after master reset. |+| 32 | RTS | output | Request to send is active (low) when set by the RTS MCR bit, inactive (high) after master reset, and is controlled by receiver threshold logic in auto-RTS mode. |+| 33 | DTR | output | Data terminal ready is active (low) when the DTR MCR bit is set and inactive after master reset, loop mode, or clearing the DTR bit. |+| 34 | OUT1 | output | User-designated output 1 is forced low when MCR bit 2 is set and high when cleared, and is high after master reset. |+| 35 | MR | input | Master reset: when active (high) it clears most ACE registers and sets the levels of various output signals. |+| 36 | NC | unconnected | No internal connection; leave this pin unconnected. |+| 37 | NC | unconnected | No internal connection; leave this pin unconnected. |+| 38 | CTS | input | Clear to send is a modem status input that also controls the transmitter in auto-CTS mode. |+| 39 | DSR | input | Data set ready is a modem status input whose condition is read from MSR bit 5 and which generates an interrupt on change when enabled. |+| 40 | DCD | input | Data carrier detect is a modem status input whose condition is read from MSR bit 7 and which generates an interrupt on change when enabled. |+| 41 | RI | input | Ring indicator is a modem status input whose condition is read from MSR bit 6 and which generates an interrupt on a low-to-high transition when enabled. |+| 42 | VCC | power_in | Power supply input, 2.25 V to 5.5 V. |+| 43 | D0 | bidirectional | Data bus line D0 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 44 | D1 | bidirectional | Data bus line D1 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 45 | D2 | bidirectional | Data bus line D2 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 46 | D3 | bidirectional | Data bus line D3 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 47 | D4 | bidirectional | Data bus line D4 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU. |+| 48 | NC | unconnected | No internal connection; leave this pin unconnected. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-48(7x7) |+| Category | Interface |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `TL16C550DPTR`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `tl16c550dptr-etched.step` / `tl16c550dptr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tl16c550dptr.step` / `tl16c550dptr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tl16c550d) (60 pp, sha256 `a49ab32dac5b1c13`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tl16c550dptr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "tl16c550dptr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tl16c550dptr.kicad_sym",+ "tl16c550dptr.kicad_mod",+ "tl16c550dptr.glb",+ "tl16c550dptr.step",+ "tl16c550dptr.lbr",+ "docs/hero.png",+ "docs/tl16c550dptr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tl16c550dptr-hero.glb",+ "tl16c550dptr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TL16C550DPTR",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Interface",+ "subcategory": "UART",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tl16c550d",+ "parts": {+ "symbol": "tl16c550dptr.kicad_sym",+ "footprint": "tl16c550dptr.kicad_mod",+ "model_3d": "tl16c550dptr-hero.glb",+ "model_3d_plain": "tl16c550dptr.glb",+ "model_3d_step": "tl16c550dptr-etched.step",+ "model_3d_step_plain": "tl16c550dptr.step",+ "lbr": "tl16c550dptr.lbr"+ },+ "distributor_links": {+ "lcsc": "C544406",+ "digikey": "296-TL16C550DPTR-ND",+ "mouser": "595-TL16C550DPTR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T23:43:20Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-TL16C550DPTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TL16C550DPTR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ },+ {+ "number": "2",+ "name": "D5",+ "type": "bidirectional",+ "description": "Data bus line D5 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "3",+ "name": "D6",+ "type": "bidirectional",+ "description": "Data bus line D6 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "4",+ "name": "D7",+ "type": "bidirectional",+ "description": "Data bus line D7 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "5",+ "name": "RCLK",+ "type": "input",+ "description": "Receiver clock is the 16x baud rate clock for the receiver section of the ACE."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ },+ {+ "number": "7",+ "name": "SIN",+ "type": "input",+ "description": "Serial data input receives serial data from the connected communications device."+ },+ {+ "number": "8",+ "name": "SOUT",+ "type": "output",+ "description": "Serial data output sends composite serial data to the connected communication device and is set to marking (high) by master reset."+ },+ {+ "number": "9",+ "name": "CS0",+ "type": "input",+ "description": "Chip select 0: with CS1 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive."+ },+ {+ "number": "10",+ "name": "CS1",+ "type": "input",+ "description": "Chip select 1: with CS0 high and CS2 low, these inputs select the ACE; when any chip select is inactive the ACE remains inactive."+ },+ {+ "number": "11",+ "name": "CS2",+ "type": "input",+ "description": "Chip select 2: with CS0 and CS1 high and CS2 low, this input selects the ACE; when inactive the ACE remains inactive."+ },+ {+ "number": "12",+ "name": "BAUDOUT",+ "type": "output",+ "description": "Baud out provides a 16x transmitter clock whose rate is set by the reference oscillator divided by the baud generator divisor; it may be tied to RCLK for receiver clocking."+ },+ {+ "number": "13",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ },+ {+ "number": "14",+ "name": "XIN",+ "type": "bidirectional",+ "description": "External clock input connects the ACE to the main timing reference (clock or crystal) together with XOUT."+ },+ {+ "number": "15",+ "name": "XOUT",+ "type": "bidirectional",+ "description": "External clock output connects the ACE to the main timing reference (crystal) together with XIN."+ },+ {+ "number": "16",+ "name": "WR1",+ "type": "input",+ "description": "Write input 1: when active (low) with WR2 tied inactive (high) and the ACE selected, the CPU may write control words or data."+ },+ {+ "number": "17",+ "name": "WR2",+ "type": "input",+ "description": "Write input 2: when active (high) with WR1 tied inactive (low) and the ACE selected, the CPU may write control words or data."+ },+ {+ "number": "18",+ "name": "VSS",+ "type": "power_in",+ "description": "Supply common (ground) for the device."+ },+ {+ "number": "19",+ "name": "RD1",+ "type": "input",+ "description": "Read input 1: when active (low) with the ACE selected, the CPU may read status or data from the selected ACE register; RD2 must be tied to its inactive level."+ },+ {+ "number": "20",+ "name": "RD2",+ "type": "input",+ "description": "Read input 2: when active (high) with the ACE selected, the CPU may read status or data from the selected ACE register; RD1 must be tied to its inactive level."+ },+ {+ "number": "21",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ },+ {+ "number": "22",+ "name": "DDIS",+ "type": "output",+ "description": "Driver disable is active (high) when the CPU is not reading data and can disable an external transceiver."+ },+ {+ "number": "23",+ "name": "TXRDY",+ "type": "output",+ "description": "Transmitter ready provides transmitter DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode)."+ },+ {+ "number": "24",+ "name": "ADS",+ "type": "input",+ "description": "Address strobe: when active (low), A0-A2 and CS0-CS2 drive the select logic directly; when high, they are held at their levels at the low-to-high ADS transition."+ },+ {+ "number": "25",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ },+ {+ "number": "26",+ "name": "A2",+ "type": "input",+ "description": "Register select bit 2 selects the ACE register for read or write operations (see Table 1)."+ },+ {+ "number": "27",+ "name": "A1",+ "type": "input",+ "description": "Register select bit 1 selects the ACE register for read or write operations (see Table 1)."+ },+ {+ "number": "28",+ "name": "A0",+ "type": "input",+ "description": "Register select bit 0 selects the ACE register for read or write operations (see Table 1)."+ },+ {+ "number": "29",+ "name": "RXRDY",+ "type": "output",+ "description": "Receiver ready provides receiver DMA signaling (mode 0 single transfer or mode 1 multitransfer, selected by FCR3 in FIFO mode) and goes active low when data is available."+ },+ {+ "number": "30",+ "name": "INTRPT",+ "type": "output",+ "description": "Interrupt output is active (high) to inform the CPU of a receiver error, received data, an empty transmitter holding register or a modem status interrupt."+ },+ {+ "number": "31",+ "name": "OUT2",+ "type": "output",+ "description": "User-designated output 2 is forced low when MCR bit 3 is set and high when cleared, and is high after master reset."+ },+ {+ "number": "32",+ "name": "RTS",+ "type": "output",+ "description": "Request to send is active (low) when set by the RTS MCR bit, inactive (high) after master reset, and is controlled by receiver threshold logic in auto-RTS mode."+ },+ {+ "number": "33",+ "name": "DTR",+ "type": "output",+ "description": "Data terminal ready is active (low) when the DTR MCR bit is set and inactive after master reset, loop mode, or clearing the DTR bit."+ },+ {+ "number": "34",+ "name": "OUT1",+ "type": "output",+ "description": "User-designated output 1 is forced low when MCR bit 2 is set and high when cleared, and is high after master reset."+ },+ {+ "number": "35",+ "name": "MR",+ "type": "input",+ "description": "Master reset: when active (high) it clears most ACE registers and sets the levels of various output signals."+ },+ {+ "number": "36",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ },+ {+ "number": "37",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ },+ {+ "number": "38",+ "name": "CTS",+ "type": "input",+ "description": "Clear to send is a modem status input that also controls the transmitter in auto-CTS mode."+ },+ {+ "number": "39",+ "name": "DSR",+ "type": "input",+ "description": "Data set ready is a modem status input whose condition is read from MSR bit 5 and which generates an interrupt on change when enabled."+ },+ {+ "number": "40",+ "name": "DCD",+ "type": "input",+ "description": "Data carrier detect is a modem status input whose condition is read from MSR bit 7 and which generates an interrupt on change when enabled."+ },+ {+ "number": "41",+ "name": "RI",+ "type": "input",+ "description": "Ring indicator is a modem status input whose condition is read from MSR bit 6 and which generates an interrupt on a low-to-high transition when enabled."+ },+ {+ "number": "42",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply input, 2.25 V to 5.5 V."+ },+ {+ "number": "43",+ "name": "D0",+ "type": "bidirectional",+ "description": "Data bus line D0 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "44",+ "name": "D1",+ "type": "bidirectional",+ "description": "Data bus line D1 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "45",+ "name": "D2",+ "type": "bidirectional",+ "description": "Data bus line D2 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "46",+ "name": "D3",+ "type": "bidirectional",+ "description": "Data bus line D3 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "47",+ "name": "D4",+ "type": "bidirectional",+ "description": "Data bus line D4 provides a bidirectional 3-state path for data, control and status between the ACE and the CPU."+ },+ {+ "number": "48",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave this pin unconnected."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package match: the ordering table (pages 43-44) lists TL16C550DPTR as LQFP (PT), 48 pins, 0 to 70 °C; XIN and XOUT are labeled I/O in the datasheet, so they are typed bidirectional as printed. Verify th; Pins 1, 6, 13, 21, 25, 36, 37 and 48 are all printed as NC in the datasheet and are listed individua"+ ],+ "pages_sent": 18,+ "cost_usd": 0.1435,+ "at": "2026-10-07T23:42:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tl16c550d",+ "pages": 60,+ "sha256": "a49ab32dac5b1c13",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tl16c550dptr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tl16c550dptr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "741814600dbd89ae862489b0c3f9e23d44c28c967712318a1e45c7a761f51632",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}