# TL16C550DPT

**Texas Instruments** · UART · QFP-48(7x7)

TL16C550DPT from Texas Instruments, in a QFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | D5 | bidirectional | Data bus line D5; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 3 | D6 | bidirectional | Data bus line D6; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 4 | D7 | bidirectional | Data bus line D7; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 5 | RCLK | input | Receiver clock, the 16× baud rate clock for the receiver section of the ACE. |
| 6 | NC | unconnected | No internal connection. |
| 7 | SIN | input | Serial data input from a connected communications device. |
| 8 | SOUT | output | Composite serial data output to a connected communication device; it is set to the marking (high) level as a result of master reset. |
| 9 | CS0 | input | Chip select; when CS0 and CS1 are high and CS2 is low the ACE is selected, and when any of these inputs is inactive the ACE remains inactive. |
| 10 | CS1 | input | Chip select; when CS0 and CS1 are high and CS2 is low the ACE is selected, and when any of these inputs is inactive the ACE remains inactive. |
| 11 | CS2 | input | Chip select; when CS0 and CS1 are high and CS2 is low the ACE is selected, and when any of these inputs is inactive the ACE remains inactive. |
| 12 | BAUDOUT | output | 16× clock for the transmitter section, set by the reference oscillator frequency divided by the baud generator divisor; it may be tied to RCLK for receiver use. |
| 13 | NC | unconnected | No internal connection. |
| 14 | XIN | bidirectional | XIN and XOUT connect the ACE to the main timing reference (clock or crystal). |
| 15 | XOUT | bidirectional | XIN and XOUT connect the ACE to the main timing reference (clock or crystal). |
| 16 | WR1 | input | Write input; when WR1 is active (low) and the ACE is selected, the CPU may write control words or data into a selected ACE register, with only one of WR1 or WR2 required. |
| 17 | WR2 | input | Write input; when WR2 is active (high) and the ACE is selected, the CPU may write control words or data into a selected ACE register, with the other write input tied to its inactive level. |
| 18 | VSS | power_in | Supply common (ground). |
| 19 | RD1 | input | Read input; when RD1 is active (low) while the ACE is selected, the CPU may read status information or data from a selected ACE register. |
| 20 | RD2 | input | Read input; when RD2 is active (high) while the ACE is selected, the CPU may read status information or data, with the other read input tied to its inactive level. |
| 21 | NC | unconnected | No internal connection. |
| 22 | DDIS | output | Driver disable; active (high) when the CPU is not reading data, and can be used to disable an external transceiver. |
| 23 | TXRDY | output | Transmitter DMA signaling; in DMA mode 0 a transfer is made between CPU bus cycles, and in DMA mode 1 transfers continue until the transmit FIFO is filled. |
| 24 | ADS | input | Address strobe; when ADS is active (low), A0-A2 and CS0-CS2 drive the internal select logic directly, and when high these levels are held from the low-to-high transition. |
| 25 | NC | unconnected | No internal connection. |
| 26 | A2 | input | Register select; A0-A2 select the ACE register to read from or write to, per the register address table. |
| 27 | A1 | input | Register select; A0-A2 select the ACE register to read from or write to, per the register address table. |
| 28 | A0 | input | Register select; A0-A2 select the ACE register to read from or write to, per the register address table. |
| 29 | RXRDY | output | Receiver DMA signaling; in DMA mode 0 it goes active (low) when at least one character is in the receiver FIFO or holding register. |
| 30 | INTRPT | output | Interrupt; when active (high) it informs the CPU that the ACE has an interrupt to be serviced. |
| 31 | OUT2 | output | User-designated output 2; it is set active (low) by MCR bit 3 and forced inactive (high) by master reset, loop mode, or clearing that bit. |
| 32 | RTS | output | Request to send; it is set active by the RTS MCR bit and set inactive (high) by master reset, loop mode, or clearing MCR bit 1, and is controlled by the receiver threshold logic in auto-RTS mode. |
| 33 | DTR | output | Data terminal ready; when active (low) it informs a modem or data set that the ACE is ready to establish communication. |
| 34 | OUT1 | output | User-designated output 1; it is set active (low) by MCR bit 2 and forced inactive (high) by master reset, loop mode, or clearing that bit. |
| 35 | MR | input | Master reset; when active (high) it clears most ACE registers and sets the levels of various output signals. |
| 36 | NC | unconnected | No internal connection. |
| 37 | NC | unconnected | No internal connection. |
| 38 | CTS | input | Clear to send modem status signal, readable at MSR bit 4, and also used in auto-CTS mode to control the transmitter. |
| 39 | DSR | input | Data set ready modem status signal, readable at MSR bit 5, which generates an interrupt on change when the modem status interrupt is enabled. |
| 40 | DCD | input | Data carrier detect modem status signal, readable at MSR bit 7, which generates an interrupt on change when the modem status interrupt is enabled. |
| 41 | RI | input | Ring indicator modem status signal, readable at MSR bit 6, with a trailing-edge change flagged in MSR bit 2 when the modem status interrupt is enabled. |
| 42 | VCC | power_in | Power supply voltage, 2.25 V to 5.5 V. |
| 43 | D0 | bidirectional | Data bus line D0; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 44 | D1 | bidirectional | Data bus line D1; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 45 | D2 | bidirectional | Data bus line D2; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 46 | D3 | bidirectional | Data bus line D3; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 47 | D4 | bidirectional | Data bus line D4; the eight data lines with 3-state outputs form a bidirectional path for data, control and status information between the ACE and the CPU. |
| 48 | NC | unconnected | No internal connection. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFP-48(7x7) |
| Category | Interface |
| Pins | 48 |

## CAD (KiCad official)

- Symbol: `TL16C550DPT`
- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`
- 3D model: QFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `tl16c550dpt-etched.step` / `tl16c550dpt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tl16c550dpt.step` / `tl16c550dpt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tl16c550d) (60 pp, sha256 `a49ab32dac5b1c13`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tl16c550dpt-datasheet.pdf)