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TL16C550DPFBR

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Texas Instruments UART, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TL16C550DPFBR

Texas Instruments · UART · TQFP-48(7x7)

TL16C550DPFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; leave unconnected.
2 D5 bidirectional Data bus bit 5 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
3 D6 bidirectional Data bus bit 6 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
4 D7 bidirectional Data bus bit 7 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
5 RCLK input Receiver clock, the 16x baud rate clock for the receiver section of the ACE.
6 NC unconnected No internal connection; leave unconnected.
7 SIN input Serial data input from the connected communications device.
8 SOUT output Composite serial data output to the connected communication device; set to the marking (high) level by master reset.
9 CS0 input Chip select 0; with CS1 high and CS2 low it selects the ACE, and when inactive the ACE remains inactive.
10 CS1 input Chip select 1; with CS0 high and CS2 low it selects the ACE, and when inactive the ACE remains inactive.
11 CS2 input Chip select 2; with CS0 and CS1 high and CS2 low the ACE is selected, and when inactive the ACE remains inactive.
12 BAUDOUT output 16x transmitter clock output set by the baud generator divisor; can be tied to RCLK to clock the receiver.
13 NC unconnected No internal connection; leave unconnected.
14 XIN bidirectional External clock input; XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
15 XOUT bidirectional Crystal/oscillator output; XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
16 WR1 input Write input 1; when active (low) with the ACE selected, the CPU writes control words or data into the ACE.
17 WR2 input Write input 2; when active (high) with the ACE selected, the CPU writes control words or data into the ACE; tie to its inactive level (low) if unused.
18 VSS power_in Supply common (ground) for the device.
19 RD1 input Read input 1; when active (low) with the ACE selected, the CPU reads status or data from the selected ACE register.
20 RD2 input Read input 2; when active (high) with the ACE selected, the CPU reads status or data; tie to its inactive level (low) if unused.
21 NC unconnected No internal connection; leave unconnected.
22 DDIS output Driver disable; active (high) when the CPU is not reading data, and can disable an external transceiver.
23 TXRDY output Transmitter DMA ready signal; in DMA mode 0 it signals single transfers, in mode 1 multiple transfers until the transmit FIFO is full.
24 ADS input Address strobe; when active (low) A0-A2 and CS0-CS2 drive the select logic directly, and when high the register and chip select levels are held.
25 NC unconnected No internal connection; leave unconnected.
26 A2 input Register select bit 2; selects the ACE register for read and write operations (see Table 1 and ADS).
27 A1 input Register select bit 1; selects the ACE register for read and write operations (see Table 1 and ADS).
28 A0 input Register select bit 0; selects the ACE register for read and write operations (see Table 1 and ADS).
29 RXRDY output Receiver DMA ready signal; active (low) when characters are available in the FIFO or holding register, with mode 0 or mode 1 selected by FCR3.
30 INTRPT output Interrupt output; active (high) to tell the CPU the ACE has an interrupt to be serviced, cleared on service or master reset.
31 OUT2 output User-designated output 2, forced low when MCR bit 3 is set and high when cleared; high after master reset.
32 RTS output Request to send; active when set by the RTS MCR bit, inactive (high) after master reset, and driven by receiver threshold logic in auto-RTS mode.
33 DTR output Data terminal ready; active (low) when the DTR MCR bit is set, and inactive (high) after master reset, loop mode or clearing the bit.
34 OUT1 output User-designated output 1, forced low when MCR bit 2 is set and high when cleared; high after master reset.
35 MR input Master reset; when active (high) it clears most ACE registers and sets the levels of various output signals.
36 NC unconnected No internal connection; leave unconnected.
37 NC unconnected No internal connection; leave unconnected.
38 CTS input Clear to send modem status input; controls the transmitter in auto-CTS mode and raises an interrupt on change when auto-CTS is off.
39 DSR input Data set ready modem status input; its state is read via MSR bit 5 and a change can raise a modem status interrupt.
40 DCD input Data carrier detect modem status input; its state is read via MSR bit 7 and a change can raise a modem status interrupt.
41 RI input Ring indicator modem status input; its state is read via MSR bit 6 and a low-to-high transition sets TERI.
42 VCC power_in Power supply, 2.25 V to 5.5 V.
43 D0 bidirectional Data bus bit 0 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
44 D1 bidirectional Data bus bit 1 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
45 D2 bidirectional Data bus bit 2 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
46 D3 bidirectional Data bus bit 3 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
47 D4 bidirectional Data bus bit 4 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU.
48 NC unconnected No internal connection; leave unconnected.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: TL16C550DPFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: tl16c550dpfbr-etched.step / tl16c550dpfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl16c550dpfbr.step / tl16c550dpfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 a49ab32dac5b1c13, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF