component
TL16C550DPFBR
Public Made by Adomby adom
Texas Instruments UART, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+84@@ -0,0 +1,84 @@+# TL16C550DPFBR++**Texas Instruments** · UART · TQFP-48(7x7)++TL16C550DPFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | No internal connection; leave unconnected. |+| 2 | D5 | bidirectional | Data bus bit 5 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 3 | D6 | bidirectional | Data bus bit 6 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 4 | D7 | bidirectional | Data bus bit 7 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 5 | RCLK | input | Receiver clock, the 16x baud rate clock for the receiver section of the ACE. |+| 6 | NC | unconnected | No internal connection; leave unconnected. |+| 7 | SIN | input | Serial data input from the connected communications device. |+| 8 | SOUT | output | Composite serial data output to the connected communication device; set to the marking (high) level by master reset. |+| 9 | CS0 | input | Chip select 0; with CS1 high and CS2 low it selects the ACE, and when inactive the ACE remains inactive. |+| 10 | CS1 | input | Chip select 1; with CS0 high and CS2 low it selects the ACE, and when inactive the ACE remains inactive. |+| 11 | CS2 | input | Chip select 2; with CS0 and CS1 high and CS2 low the ACE is selected, and when inactive the ACE remains inactive. |+| 12 | BAUDOUT | output | 16x transmitter clock output set by the baud generator divisor; can be tied to RCLK to clock the receiver. |+| 13 | NC | unconnected | No internal connection; leave unconnected. |+| 14 | XIN | bidirectional | External clock input; XIN and XOUT connect the ACE to the main timing reference (clock or crystal). |+| 15 | XOUT | bidirectional | Crystal/oscillator output; XIN and XOUT connect the ACE to the main timing reference (clock or crystal). |+| 16 | WR1 | input | Write input 1; when active (low) with the ACE selected, the CPU writes control words or data into the ACE. |+| 17 | WR2 | input | Write input 2; when active (high) with the ACE selected, the CPU writes control words or data into the ACE; tie to its inactive level (low) if unused. |+| 18 | VSS | power_in | Supply common (ground) for the device. |+| 19 | RD1 | input | Read input 1; when active (low) with the ACE selected, the CPU reads status or data from the selected ACE register. |+| 20 | RD2 | input | Read input 2; when active (high) with the ACE selected, the CPU reads status or data; tie to its inactive level (low) if unused. |+| 21 | NC | unconnected | No internal connection; leave unconnected. |+| 22 | DDIS | output | Driver disable; active (high) when the CPU is not reading data, and can disable an external transceiver. |+| 23 | TXRDY | output | Transmitter DMA ready signal; in DMA mode 0 it signals single transfers, in mode 1 multiple transfers until the transmit FIFO is full. |+| 24 | ADS | input | Address strobe; when active (low) A0-A2 and CS0-CS2 drive the select logic directly, and when high the register and chip select levels are held. |+| 25 | NC | unconnected | No internal connection; leave unconnected. |+| 26 | A2 | input | Register select bit 2; selects the ACE register for read and write operations (see Table 1 and ADS). |+| 27 | A1 | input | Register select bit 1; selects the ACE register for read and write operations (see Table 1 and ADS). |+| 28 | A0 | input | Register select bit 0; selects the ACE register for read and write operations (see Table 1 and ADS). |+| 29 | RXRDY | output | Receiver DMA ready signal; active (low) when characters are available in the FIFO or holding register, with mode 0 or mode 1 selected by FCR3. |+| 30 | INTRPT | output | Interrupt output; active (high) to tell the CPU the ACE has an interrupt to be serviced, cleared on service or master reset. |+| 31 | OUT2 | output | User-designated output 2, forced low when MCR bit 3 is set and high when cleared; high after master reset. |+| 32 | RTS | output | Request to send; active when set by the RTS MCR bit, inactive (high) after master reset, and driven by receiver threshold logic in auto-RTS mode. |+| 33 | DTR | output | Data terminal ready; active (low) when the DTR MCR bit is set, and inactive (high) after master reset, loop mode or clearing the bit. |+| 34 | OUT1 | output | User-designated output 1, forced low when MCR bit 2 is set and high when cleared; high after master reset. |+| 35 | MR | input | Master reset; when active (high) it clears most ACE registers and sets the levels of various output signals. |+| 36 | NC | unconnected | No internal connection; leave unconnected. |+| 37 | NC | unconnected | No internal connection; leave unconnected. |+| 38 | CTS | input | Clear to send modem status input; controls the transmitter in auto-CTS mode and raises an interrupt on change when auto-CTS is off. |+| 39 | DSR | input | Data set ready modem status input; its state is read via MSR bit 5 and a change can raise a modem status interrupt. |+| 40 | DCD | input | Data carrier detect modem status input; its state is read via MSR bit 7 and a change can raise a modem status interrupt. |+| 41 | RI | input | Ring indicator modem status input; its state is read via MSR bit 6 and a low-to-high transition sets TERI. |+| 42 | VCC | power_in | Power supply, 2.25 V to 5.5 V. |+| 43 | D0 | bidirectional | Data bus bit 0 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 44 | D1 | bidirectional | Data bus bit 1 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 45 | D2 | bidirectional | Data bus bit 2 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 46 | D3 | bidirectional | Data bus bit 3 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 47 | D4 | bidirectional | Data bus bit 4 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU. |+| 48 | NC | unconnected | No internal connection; leave unconnected. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-48(7x7) |+| Category | Interface |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `TL16C550DPFBR`+- Footprint: `Package_QFP:TQFP-48_7x7mm_P0.5mm`+- 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `tl16c550dpfbr-etched.step` / `tl16c550dpfbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tl16c550dpfbr.step` / `tl16c550dpfbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tl16c550d) (60 pp, sha256 `a49ab32dac5b1c13`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tl16c550dpfbr-datasheet.pdf)
page.jsonadded+440@@ -0,0 +1,440 @@+{+ "slug": "tl16c550dpfbr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments UART, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "tl16c550dpfbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tl16c550dpfbr.kicad_sym",+ "tl16c550dpfbr.kicad_mod",+ "tl16c550dpfbr.glb",+ "tl16c550dpfbr.step",+ "tl16c550dpfbr.lbr",+ "docs/hero.png",+ "docs/tl16c550dpfbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tl16c550dpfbr-hero.glb",+ "tl16c550dpfbr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TL16C550DPFBR",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-48(7x7)",+ "pin_count": 48,+ "category": "Interface",+ "subcategory": "UART",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tl16c550d",+ "parts": {+ "symbol": "tl16c550dpfbr.kicad_sym",+ "footprint": "tl16c550dpfbr.kicad_mod",+ "model_3d": "tl16c550dpfbr-hero.glb",+ "model_3d_plain": "tl16c550dpfbr.glb",+ "model_3d_step": "tl16c550dpfbr-etched.step",+ "model_3d_step_plain": "tl16c550dpfbr.step",+ "lbr": "tl16c550dpfbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2653243",+ "digikey": "296-TL16C550DPFBRTR-ND",+ "mouser": "595-TL16C550DPFBR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:47:16Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-TL16C550DPFBRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TL16C550DPFBR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ },+ {+ "number": "2",+ "name": "D5",+ "type": "bidirectional",+ "description": "Data bus bit 5 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "3",+ "name": "D6",+ "type": "bidirectional",+ "description": "Data bus bit 6 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "4",+ "name": "D7",+ "type": "bidirectional",+ "description": "Data bus bit 7 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "5",+ "name": "RCLK",+ "type": "input",+ "description": "Receiver clock, the 16x baud rate clock for the receiver section of the ACE."+ },+ {+ "number": "6",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ },+ {+ "number": "7",+ "name": "SIN",+ "type": "input",+ "description": "Serial data input from the connected communications device."+ },+ {+ "number": "8",+ "name": "SOUT",+ "type": "output",+ "description": "Composite serial data output to the connected communication device; set to the marking (high) level by master reset."+ },+ {+ "number": "9",+ "name": "CS0",+ "type": "input",+ "description": "Chip select 0; with CS1 high and CS2 low it selects the ACE, and when inactive the ACE remains inactive."+ },+ {+ "number": "10",+ "name": "CS1",+ "type": "input",+ "description": "Chip select 1; with CS0 high and CS2 low it selects the ACE, and when inactive the ACE remains inactive."+ },+ {+ "number": "11",+ "name": "CS2",+ "type": "input",+ "description": "Chip select 2; with CS0 and CS1 high and CS2 low the ACE is selected, and when inactive the ACE remains inactive."+ },+ {+ "number": "12",+ "name": "BAUDOUT",+ "type": "output",+ "description": "16x transmitter clock output set by the baud generator divisor; can be tied to RCLK to clock the receiver."+ },+ {+ "number": "13",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ },+ {+ "number": "14",+ "name": "XIN",+ "type": "bidirectional",+ "description": "External clock input; XIN and XOUT connect the ACE to the main timing reference (clock or crystal)."+ },+ {+ "number": "15",+ "name": "XOUT",+ "type": "bidirectional",+ "description": "Crystal/oscillator output; XIN and XOUT connect the ACE to the main timing reference (clock or crystal)."+ },+ {+ "number": "16",+ "name": "WR1",+ "type": "input",+ "description": "Write input 1; when active (low) with the ACE selected, the CPU writes control words or data into the ACE."+ },+ {+ "number": "17",+ "name": "WR2",+ "type": "input",+ "description": "Write input 2; when active (high) with the ACE selected, the CPU writes control words or data into the ACE; tie to its inactive level (low) if unused."+ },+ {+ "number": "18",+ "name": "VSS",+ "type": "power_in",+ "description": "Supply common (ground) for the device."+ },+ {+ "number": "19",+ "name": "RD1",+ "type": "input",+ "description": "Read input 1; when active (low) with the ACE selected, the CPU reads status or data from the selected ACE register."+ },+ {+ "number": "20",+ "name": "RD2",+ "type": "input",+ "description": "Read input 2; when active (high) with the ACE selected, the CPU reads status or data; tie to its inactive level (low) if unused."+ },+ {+ "number": "21",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ },+ {+ "number": "22",+ "name": "DDIS",+ "type": "output",+ "description": "Driver disable; active (high) when the CPU is not reading data, and can disable an external transceiver."+ },+ {+ "number": "23",+ "name": "TXRDY",+ "type": "output",+ "description": "Transmitter DMA ready signal; in DMA mode 0 it signals single transfers, in mode 1 multiple transfers until the transmit FIFO is full."+ },+ {+ "number": "24",+ "name": "ADS",+ "type": "input",+ "description": "Address strobe; when active (low) A0-A2 and CS0-CS2 drive the select logic directly, and when high the register and chip select levels are held."+ },+ {+ "number": "25",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ },+ {+ "number": "26",+ "name": "A2",+ "type": "input",+ "description": "Register select bit 2; selects the ACE register for read and write operations (see Table 1 and ADS)."+ },+ {+ "number": "27",+ "name": "A1",+ "type": "input",+ "description": "Register select bit 1; selects the ACE register for read and write operations (see Table 1 and ADS)."+ },+ {+ "number": "28",+ "name": "A0",+ "type": "input",+ "description": "Register select bit 0; selects the ACE register for read and write operations (see Table 1 and ADS)."+ },+ {+ "number": "29",+ "name": "RXRDY",+ "type": "output",+ "description": "Receiver DMA ready signal; active (low) when characters are available in the FIFO or holding register, with mode 0 or mode 1 selected by FCR3."+ },+ {+ "number": "30",+ "name": "INTRPT",+ "type": "output",+ "description": "Interrupt output; active (high) to tell the CPU the ACE has an interrupt to be serviced, cleared on service or master reset."+ },+ {+ "number": "31",+ "name": "OUT2",+ "type": "output",+ "description": "User-designated output 2, forced low when MCR bit 3 is set and high when cleared; high after master reset."+ },+ {+ "number": "32",+ "name": "RTS",+ "type": "output",+ "description": "Request to send; active when set by the RTS MCR bit, inactive (high) after master reset, and driven by receiver threshold logic in auto-RTS mode."+ },+ {+ "number": "33",+ "name": "DTR",+ "type": "output",+ "description": "Data terminal ready; active (low) when the DTR MCR bit is set, and inactive (high) after master reset, loop mode or clearing the bit."+ },+ {+ "number": "34",+ "name": "OUT1",+ "type": "output",+ "description": "User-designated output 1, forced low when MCR bit 2 is set and high when cleared; high after master reset."+ },+ {+ "number": "35",+ "name": "MR",+ "type": "input",+ "description": "Master reset; when active (high) it clears most ACE registers and sets the levels of various output signals."+ },+ {+ "number": "36",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ },+ {+ "number": "37",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ },+ {+ "number": "38",+ "name": "CTS",+ "type": "input",+ "description": "Clear to send modem status input; controls the transmitter in auto-CTS mode and raises an interrupt on change when auto-CTS is off."+ },+ {+ "number": "39",+ "name": "DSR",+ "type": "input",+ "description": "Data set ready modem status input; its state is read via MSR bit 5 and a change can raise a modem status interrupt."+ },+ {+ "number": "40",+ "name": "DCD",+ "type": "input",+ "description": "Data carrier detect modem status input; its state is read via MSR bit 7 and a change can raise a modem status interrupt."+ },+ {+ "number": "41",+ "name": "RI",+ "type": "input",+ "description": "Ring indicator modem status input; its state is read via MSR bit 6 and a low-to-high transition sets TERI."+ },+ {+ "number": "42",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply, 2.25 V to 5.5 V."+ },+ {+ "number": "43",+ "name": "D0",+ "type": "bidirectional",+ "description": "Data bus bit 0 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "44",+ "name": "D1",+ "type": "bidirectional",+ "description": "Data bus bit 1 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "45",+ "name": "D2",+ "type": "bidirectional",+ "description": "Data bus bit 2 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "46",+ "name": "D3",+ "type": "bidirectional",+ "description": "Data bus bit 3 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "47",+ "name": "D4",+ "type": "bidirectional",+ "description": "Data bus bit 4 of the eight 3-state data lines that carry data, control and status between the ACE and the CPU."+ },+ {+ "number": "48",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection; leave unconnected."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The PT/PFB pin diagram in the extracted text is garbled, so the pin-to-number mapping was taken from; The 7x7 mm body size is from the package hint only; the extracted text does not state the package di; Pin 1 and pins 6, 13, 21, 25, 36, 37 and 48 are listed as NC (no internal connection) in the PT/PFB "+ ],+ "pages_sent": 18,+ "cost_usd": 0.1446,+ "at": "2026-10-08T15:46:50"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tl16c550d",+ "pages": 60,+ "sha256": "a49ab32dac5b1c13",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tl16c550dpfbr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "14ca7676e4932e92f0eca0c6d56ce3018cd28a2531204a70ab7bbacb3eeb3cf5",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tl16c550dpfbr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0020a31b8c43164214672fd7b61cd9cdfe3796f7ab20815934e9987ec86275f1",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}