component

TL103WBIDR

Public Made by Adom

by adom

Texas Instruments , SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TL103WBIDR

Texas Instruments · IC · SOIC-8

TL103WBIDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OUT output Opamp 1 output.
2 1IN- input Opamp 1 inverting input.
3 1IN+ input Opamp 1 non-inverting input and shunt reference cathode terminal; the input voltage range is (VCC-) - 0.3 V to VCC+ V per the absolute maximum ratings.
4 VCC- power_in Negative supply voltage; the recommended supply range for TL103WB is 3 V to 36 V (VCC+ minus VCC-).
5 2IN+ input Opamp 2 non-inverting input.
6 2IN- input Opamp 2 inverting input.
7 2OUT output Opamp 2 output.
8 VCC+ power_in Positive supply voltage; the recommended supply range for TL103WB is 3 V to 36 V (VCC+ minus VCC-), with an absolute maximum of 40 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (TL103WB) VCC± 0 40 V 4
Operational amplifier input differential voltage VID 36 V 4
Voltage reference cathode current IKA 100 mA 4
Maximum junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
ESD human body model (HBM) V(ESD) -2500 2500 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 4
Supply voltage (TL103WB) VCC± 3 36 V 4
Cathode current (TL103WB) IK 0.2 100 mA 4
Operating free-air temperature (TL103WB) TA -40 125 °C 4
Input offset voltage, OP AMP1 (25°C) VIO -2 0.3 2 mV VICM = 0V; TA = 25°C 5
Input offset voltage, OP AMP1 (full range) VIO -2.5 2.5 mV VICM = 0V; full range 5
Input offset-voltage drift, OP AMP1 αVIO -2 2 µV/°C Full range 5
Supply-voltage rejection ratio, OP AMP1 PSRR 99 114 dB VCC+ = 5V to 30V, VICM = 0V 5
Output current, source, OP AMP1 IO 20 40 mA VCC+ = 15V, VO = 2V, VID = 1V; source 5
Output current, sink, OP AMP1 IO 10 24 mA VCC+ = 15V, VO = 2V, VID = 1V; sink 5
Output current, sink, OP AMP1 (low VO) IO 60 100 µA VCC+ = 15V, VO = 0.2V, VID = -1V; sink 5
Short-circuit current to GND, OP AMP1 ISC -68 40 68 mA VCC+ = 15V 5
Output voltage swing from positive rail, OP AMP1 (25°C) VO 27.4 28.3 V VCC+ = 30V, RL = 2kΩ; 25°C 5
Output voltage swing from positive rail, OP AMP1 (full range) VO 27.4 V VCC+ = 30V, RL = 2kΩ; full range 5
Output voltage swing from positive rail, OP AMP1 (RL=10kΩ, 25°C) VO 27.6 28.6 V VCC+ = 30V, RL = 10kΩ; 25°C 5
Output voltage swing from positive rail, OP AMP1 (RL=10kΩ, full range) VO 27.6 V VCC+ = 30V, RL = 10kΩ; full range 5
Output voltage swing from negative rail, OP AMP1 (25°C) VO 5 20 mV RL = 10kΩ; 25°C 5
Output voltage swing from negative rail, OP AMP1 (full range) VO 20 mV RL = 10kΩ; full range 5
Slew rate at unity gain, OP AMP1 SR 0.2 0.5 V/µs VCC+ = 15V, CL = 100pF, RL = 2kΩ, VI = 0.5V to 2V, unity gain 5
Gain bandwidth product, OP AMP1 GBW 0.7 1.2 MHz VCC+ = 36V, VI = 10mV, CL = 100pF, RL = 2kΩ, f = 100kHz 5
Total supply current, both amplifiers (5V) ICC 0.55 0.77 mA VCC+ = 5V, no load 6
Total supply current, both amplifiers (36V, full range) ICC 1.35 mA VCC+ = 36V, no load; full range 6
Reference voltage (25°C) Vref 2.489 2.5 2.511 V IK = 10mA 6
Reference voltage (full range) Vref 2.474 2.526 V IK = 10mA; full range 6
Reference input voltage deviation over temperature range ΔVref 7 26 mV IK = 10mA; full range 6
Minimum cathode current for regulation Imin 0.2 1 mA 6
Dynamic impedance /ZKA/ 0.45 0.8 Ω IKA = 1mA to 100mA, f < 1kHz 6
Input offset voltage, OP AMP2 (25°C) VIO -2 0.3 2 mV VICM = 0V; TA = 25°C 6
Input offset voltage, OP AMP2 (full range) VIO -2.5 2.5 mV VICM = 0V; full range 6
Input offset-voltage drift, OP AMP2 αVIO -2 2 µV/°C Full range 6
Input offset current, OP AMP2 (25°C) IIO -4 0.5 4 nA 6
Input offset current, OP AMP2 (full range) IIO -5 5 nA full range 6
Input bias current, OP AMP2 (25°C) IIB -35 -15 nA 6
Input bias current, OP AMP2 (full range) IIB -50 nA full range 6
Large-signal voltage gain, OP AMP2 (25°C) AVD 77 210 V/mV VCC+ = 15V, RL = 2kΩ, VO = 1.4V to 11.4V 6
Large-signal voltage gain, OP AMP2 (full range) AVD 45 210 V/mV VCC+ = 15V, RL = 2kΩ, VO = 1.4V to 11.4V; full range 6
Supply-voltage rejection ratio, OP AMP2 PSRR 99 114 dB VCC+ = 5V to 30V 6
Common-mode rejection ratio, OP AMP2 (25°C) CMRR 93 104 dB VCC+ = 30V 6
Common-mode rejection ratio, OP AMP2 (full range) CMRR 70 dB VCC+ = 30V; full range 6
Output current, source, OP AMP2 IO 20 40 mA VCC+ = 15V, VO = 2V, VID = 1V; source 7
Output current, sink, OP AMP2 IO 10 24 mA VCC+ = 15V, VO = 2V, VID = 1V; sink 7
Output current, sink, OP AMP2 (low VO) IO 60 100 µA VCC+ = 15V, VO = 0.2V, VID = -1V; sink 7
Short-circuit current to GND, OP AMP2 ISC -68 40 68 mA VCC+ = 15V 7
Output voltage swing from positive rail, OP AMP2 (25°C) VO 27.4 28.3 V VCC+ = 30V, RL = 2kΩ; 25°C 7
Output voltage swing from positive rail, OP AMP2 (full range) VO 27.4 V VCC+ = 30V, RL = 2kΩ; full range 7
Output voltage swing from positive rail, OP AMP2 (RL=10kΩ, 25°C) VO 27.6 28.6 V VCC+ = 30V, RL = 10kΩ; 25°C 7
Output voltage swing from positive rail, OP AMP2 (RL=10kΩ, full range) VO 27.6 V VCC+ = 30V, RL = 10kΩ; full range 7
Output voltage swing from negative rail, OP AMP2 VO 5 20 mV RL = 10kΩ 7
Slew rate at unity gain, OP AMP2 SR 0.2 0.5 V/µs VCC+ = 15V, CL = 100pF, RL = 2kΩ, VI = 0.5V to 2V, unity gain 7
Gain bandwidth product, OP AMP2 GBW 0.7 1.2 MHz VCC+ = 36V, VI = 10mV, CL = 100pF, RL = 2kΩ, f = 100kHz 7
Total supply current, both amplifiers (5V, OP AMP2 table) ICC 0.55 0.77 mA VCC+ = 5V, no load 7
Total supply current, both amplifiers (36V, full range, OP AMP2 table) ICC 1.35 mA VCC+ = 36V, no load; full range 7
Junction-to-ambient thermal resistance (SOIC D) RθJA 135.4 °C/W 5
Junction-to-case (top) thermal resistance (SOIC D) RθJC(top) 77.3 °C/W 5
Junction-to-board thermal resistance (SOIC D) RθJB 78.9 °C/W 5

CAD (KiCad official)

  • Symbol: TL103WBIDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tl103wbidr-etched.step / tl103wbidr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl103wbidr.step / tl103wbidr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 07697c9c17a2fcd1, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF