component

TL082IDT

Public Made by Adom

by adom

STMicroelectronics FET InputAmplifiers, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tl082idt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json tl082idt: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wi… · Ray
README.md tl082idt: specified limits as data (metadata.characteristics, 43 rows from the datasheet) · Ray
tl082idt-etched.fit.json tl082idt: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
tl082idt-etched.glb tl082idt: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wi… · Ray
tl082idt-etched.step tl082idt: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body wi… · Ray
tl082idt.glb Publish 0.1.0 · Ray
tl082idt.kicad_mod Publish 0.1.0 · Ray
tl082idt.kicad_sym Publish 0.1.0 · Ray
tl082idt.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
tl082idt.step Publish 0.1.0 · Ray

TL082IDT

STMicroelectronics · FET InputAmplifiers · SO-8

TL082IDT from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Output of op-amp 1. Push-pull bipolar output stage with internal short-circuit protection (short to ground or either supply survives indefinitely, subject to power dissipation limits).
2 IN1- input Inverting input of op-amp 1. High-impedance JFET gate input; input voltage must not exceed the supply voltage magnitude or 15 V, whichever is less.
3 IN1+ input Non-inverting input of op-amp 1. High-impedance JFET gate input; common-mode range extends up to Vcc+.
4 VCC- power_in Negative supply rail. Typically -Vs in a split-supply configuration or GND in single-supply operation. Total supply (Vcc+ to Vcc-) range 6 to 36 V (absolute max +/-18 V).
5 IN2+ input Non-inverting input of op-amp 2. High-impedance JFET gate input; common-mode range extends up to Vcc+.
6 IN2- input Inverting input of op-amp 2. High-impedance JFET gate input; differential input voltage abs-max +/-30 V.
7 OUT2 output Output of op-amp 2. Push-pull bipolar output stage with internal short-circuit protection.
8 VCC+ power_in Positive supply rail. Typically +Vs in a split-supply configuration. Total supply (Vcc+ to Vcc-) range 6 to 36 V (absolute max +/-18 V). Bypass to VCC- with a local ceramic capacitor.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • TL082IDT
  • TL082IDTCD
  • TL082IDTCDT
  • TL082IDTACDT
  • TL082IDTBCDT
  • TL082IDTIYDT
  • TL082IDTAIYDT
  • TL082IDTBIYDT
  • TL082IDTIPT
  • TL082IDTCPT

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (recommended operating, VCC) VCC 6 36 V 5
Operating free-air temperature range (I grade) Toper -40 105 °C 5
Supply voltage (absolute maximum) VCC -18 18 V Printed as ±18 5
Input voltage (absolute maximum) Vin -15 15 V Printed as ±15; magnitude must not exceed supply voltage or 15 V, whichever is less 5
Differential input voltage (absolute maximum) Vid -30 30 V Printed as ±30 5
Power dissipation Ptot 680 mW 5
Storage temperature range Tstg -65 150 °C 5
ESD human body model ESD HBM 1 kV Human body model 5
ESD machine model ESD MM 200 V Machine model 5
ESD charged device model ESD CDM 1500 V Charged device model 5
Thermal resistance junction-to-ambient Rthja 125 °C/W SO8 package 5
Thermal resistance junction-to-case Rthjc 40 °C/W SO8 package 5
Input offset voltage (TL082) Vio 3 10 mV VCC = ±15 V, Rs = 50 Ω, Tamb = 25 °C 6
Input offset voltage over temperature (TL082) Vio 13 mV VCC = ±15 V, Rs = 50 Ω, Tmin ≤ Tamb ≤ Tmax 6
Input offset current Iio 5 100 pA VCC = ±15 V, Tamb = 25 °C 6
Input offset current over temperature Iio 4 10 nA VCC = ±15 V, Tmin ≤ Tamb ≤ Tmax 6
Input bias current Iib 20 200 pA VCC = ±15 V, Tamb = 25 °C 6
Input bias current over temperature Iib 20 nA VCC = ±15 V, Tmin ≤ Tamb ≤ Tmax 6
Large signal voltage gain Avd 50 200 V/mV VCC = ±15 V, RL = 2 kΩ, Vo = ±10 V, Tamb = 25 °C 6
Large signal voltage gain over temperature Avd 25 V/mV VCC = ±15 V, RL = 2 kΩ, Vo = ±10 V, Tmin ≤ Tamb ≤ Tmax 6
Supply voltage rejection ratio SVR 80 86 dB VCC = ±15 V, RS = 50 Ω, Tamb = 25 °C 6
Supply voltage rejection ratio over temperature SVR 80 dB VCC = ±15 V, RS = 50 Ω, Tmin ≤ Tamb ≤ Tmax 6
Supply current, no load ICC 1.4 2.5 mA VCC = ±15 V, no load, Tamb = 25 °C 6
Supply current, no load over temperature ICC 2.5 mA VCC = ±15 V, no load, Tmin ≤ Tamb ≤ Tmax 6
Input common mode voltage range Vicm -12 15 V VCC = ±15 V 6
Common mode rejection ratio CMR 80 86 dB VCC = ±15 V, RS = 50 Ω, Tamb = 25 °C 6
Common mode rejection ratio over temperature CMR 80 dB VCC = ±15 V, RS = 50 Ω, Tmin ≤ Tamb ≤ Tmax 6
Output short-circuit current Ios 10 40 60 mA VCC = ±15 V, Tamb = 25 °C 6
Output short-circuit current over temperature Ios 10 60 mA VCC = ±15 V, Tmin ≤ Tamb ≤ Tmax 6
Output voltage swing (RL = 2 kΩ) ±Vopp 10 12 V VCC = ±15 V, Tamb = 25 °C, RL = 2 kΩ 7
Output voltage swing (RL = 10 kΩ) ±Vopp 12 13.5 V VCC = ±15 V, Tamb = 25 °C, RL = 10 kΩ 7
Output voltage swing over temperature (RL = 2 kΩ) ±Vopp 10 V VCC = ±15 V, Tmin ≤ Tamb ≤ Tmax, RL = 2 kΩ 7
Output voltage swing over temperature (RL = 10 kΩ) ±Vopp 12 V VCC = ±15 V, Tmin ≤ Tamb ≤ Tmax, RL = 10 kΩ 7
Slew rate SR 8 16 V/µs VCC = ±15 V, Tamb = 25 °C, Vin = 10 V, RL = 2 kΩ, CL = 100 pF, unity gain 7
Gain bandwidth product GBP 2.5 4 MHz VCC = ±15 V, Tamb = 25 °C, Vin = 10 mV, RL = 2 kΩ, CL = 100 pF, F = 100 kHz 7
Rise time tr 0.1 µs VCC = ±15 V, Tamb = 25 °C, Vin = 20 mV, RL = 2 kΩ, CL = 100 pF, unity gain 7
Overshoot Kov 10 % VCC = ±15 V, Tamb = 25 °C, Vin = 20 mV, RL = 2 kΩ, CL = 100 pF, unity gain 7
Input resistance Ri 1012 Ω 7
Total harmonic distortion THD 0.01 % VCC = ±15 V, Tamb = 25 °C, F = 1 kHz, RL = 2 kΩ, CL = 100 pF, Av = 20 dB, Vo = 2 Vpp 7
Equivalent input noise voltage en 15 nV/√Hz VCC = ±15 V, RS = 100 Ω, F = 1 kHz 7
Phase margin ∅m 45 degrees VCC = ±15 V 7
Channel separation Vo1/Vo2 120 dB VCC = ±15 V, Av = 100 7
Input offset voltage drift DVio 10 µV/°C 6

CAD (KiCad official)

  • Symbol: TL082IDT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: tl082idt-etched.step / tl082idt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl082idt.step / tl082idt.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tl082idt.step 122 KB You want the bare part, or you mark your own boards.
tl082idt-etched.step 1.6 MB You want the part with TL082IDT already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 412 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (18 pp, sha256 040a260063ff97f8, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF