component

TL081CDTR

Public Made by Adom

by adom

XBLW TL081CDTR XBLW Operational Amplifier, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs tl081cdtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers tl081cdtr: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md tl081cdtr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 15d ago
tl081cdtr-etched.fit.json tl081cdtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tl081cdtr-etched.glb tl081cdtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tl081cdtr-etched.step tl081cdtr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
tl081cdtr.glb Publish 0.1.0 · Ray 1mo ago
tl081cdtr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tl081cdtr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tl081cdtr.lbr Publish 0.1.0 · Ray 1mo ago
tl081cdtr.step Publish 0.1.0 · Ray 1mo ago

TL081CDTR

XBLW · Operational Amplifier · SOP-8

TL081CDTR from XBLW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OFFSET N1 input Offset null pin 1. Connect an external trim potentiometer between OFFSET N1 (pin 1) and OFFSET N2 (pin 5) with the wiper tied to VCC- to null the input offset voltage (typ ±3 mV, max ±5 mV).
2 IN- input Inverting input to the JFET-input op-amp. Very high input impedance; input bias current typ ±200 nA (max), input offset current ±100 pA (max). Common-mode range (VCC-)+1.5 V to (VCC+)-0.5 V.
3 IN+ input Non-inverting input to the JFET-input op-amp. Very high input impedance; input voltage range ±15 V absolute max. Common-mode range (VCC-)+1.5 V to (VCC+)-0.5 V.
4 VCC- power_in Negative supply rail. Typically -15 V for a ±15 V split supply; absolute max supply
5 OFFSET N2 input Offset null pin 2. Used with OFFSET N1 (pin 1) and an external potentiometer (wiper to VCC-) to trim the input offset voltage to zero.
6 OUT output Op-amp output. Maximum peak output voltage swing typ ±13.5 V (min ±12 V) with RL = 10 kΩ. Internally short-circuit protected; slew rate typ 20 V/µs (min 8 V/µs), gain-bandwidth typ 3 MHz.
7 VCC+ power_in Positive supply rail. Typically +15 V for a ±15 V split supply; absolute max supply
8 NC unconnected No internal connection. Leave floating or tie to a convenient net; not electrically bonded inside the package.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • TL081CDTR
  • TL081CDTRCN

CAD (KiCad official)

  • Symbol: TL081CDTR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: tl081cdtr-etched.step / tl081cdtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl081cdtr.step / tl081cdtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (7 pp, sha256 634c075a647c4de1, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF